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MVTX2603
Unmanaged 24-Port 10/100M + 2-Port 1G Ethernet Switch
Data Sheet
Features
* * * * * * Integrated Single-Chip 10/100/1000 Mbps Ethernet Switch 24 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS) 2 Gigabit Ports with GMII, PCS, 10/100 and stacking (2G per port) interface options per port Serial interface for configuration Supports two Frame Buffer Memory domains with SRAM at 100 MHz Supports memory size 2 MB, or 4 MB
* For 24+2, two SRAM domains (2 MB or 4 MB) are required. * For 24+2 stacking (2G per stacking port), two ZBT domains (2 MB or 4 MB) are required.
February 2003
Ordering Information MVTX2603AG 553 Pin HSBGA
-40C to +85C * * Supports per-system option to enable flow control for best effort frames even on QoS-enabled ports Load sharing among trunked ports can be based on source MAC and/or destination MAC. The Gigabit trunking group has one more option, based on source port. Port Mirroring to a dedicated port or port 23 Built-in reset logic triggered by system malfunction I2C EEPROM for configuration Traffic Classification
* 4 transmission priorities for Fast Ethernet ports with 2 dropping levels * Classification based on: - Port based priority - VLAN Priority field in VLAN tagged frame
* * * * * * *
Applies centralized shared memory architecture Up to 64K MAC addresses Maximum throughput is 6.4 Gbps non-blocking High performance packet forwarding (19.047M packets per second) at full wire speed Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Supports Ethernet multicasting and broadcasting and flooding control
* * * *
VLAN 1 MCT
Frame Data Buffer A SRAM (1M / 2M)
VLAN 1 MCT
Frame Data Buffer B SRAM (1M / 2M)
FDB Interface
LED
FCB
Frame Engine
Search Engine
MCT Link
24 x 10 /100 RMII Ports 0 - 23
GMII/ PCS Port 24
GMII/ PCS Port 25
Management Module
Parallel/ Serial
Figure 1 - MVTX2603 System Block Diagram
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MVTX2603
Data Sheet
- DS/TOS field in IP packet - UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range * The precedence of the above classifications is programmable.
*
QoS Support
* Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and WFQ service disciplines * Provides 2 levels of dropping precedence with WRED mechanism * User controls the WRED thresholds. * Buffer management: per class and per port buffer reservations * Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID.
* * * * *
3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100 ports per group Full set of LED signals provided by a serial interface, or 6 LED signals dedicated to Gigabit port status only (without serial interface) Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports Built-In Self Test for internal and external SRAM
Description
The MVTX2603 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 24 ports at 10/100 Mbps, 2 ports at 1000 Mbps. The Gigabit ports can also support 10/100M and 2G stacking modes. The chip supports up to 64K MAC addresses. The centralized shared memory architecture permits a very high performance packet forwarding rate at up to 9.524M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously. In the 24+2 stacking (2G per stacking port) configuration, 2 ZBT domains are needed. With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the MVTX2603 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2603 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The MVTX2603 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports, and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The MVTX2603 also supports a persystem option to enable flow control for best effort frames, even on QoS-enabled ports. The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to SERDES chips. The PCS can be bypassed to provide a GMII interface. The MVTX2603 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The MVTX2603 is packaged in a 553-pin Ball Grid Array package.
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Data Sheet
MVTX2603 Table of Contents
1.0 Block Functionality ............................................................................................................13
1.1 Frame Data Buffer (FDB) Interfaces............................................................................................................ 13 1.2 GMII/PCS MAC Module (GMAC) ................................................................................................................ 13 1.3 Physical Coding Sublayer (PCI) Interface ................................................................................................... 13 1.4 10/100 MAC Module (RMAC)...................................................................................................................... 13 1.5 Configuration Interface Module ................................................................................................................... 14 1.6 Frame Engine .............................................................................................................................................. 14 1.7 Search Engine ............................................................................................................................................. 14 1.8 LED Interface............................................................................................................................................... 14 1.9 Internal Memory........................................................................................................................................... 14
2.0 System Configuration ........................................................................................................14
2.1 Configuration Mode ..................................................................................................................................... 14 2.2 I2C Interface ................................................................................................................................................ 14 2.2.1 Start Condition ................................................................................................................................... 14 2.2.2 Address .............................................................................................................................................. 15 2.2.3 Data Direction .................................................................................................................................... 15 2.2.4 Acknowledgment................................................................................................................................ 15 2.2.5 Data.................................................................................................................................................... 15 2.2.6 Stop Condition.................................................................................................................................... 15 2.3 Synchronous Serial Interface ...................................................................................................................... 15 2.3.1 Write Command ................................................................................................................................. 16 2.3.2 Read Command ................................................................................................................................. 16 2.4 Stacking....................................................................................................................................................... 16
3.0 MVTX2603 Data Forwarding Protocol ..............................................................................16
3.1 Unicast Data Frame Forwarding.................................................................................................................. 16 3.2 Multicast Data Frame Forwarding ............................................................................................................... 17
4.0 Memory Interface................................................................................................................18
4.1 Overview...................................................................................................................................................... 18 4.2 ZBT Support ................................................................................................................................................ 18 4.3 Detailed Memory Information ...................................................................................................................... 18 4.4 Memory Requirements ................................................................................................................................ 19
5.0 Search Engine ....................................................................................................................19
5.1 Search Engine Overview ............................................................................................................................. 19 5.2 Basic Flow ................................................................................................................................................... 19 5.3 Search, Learning, and Aging ....................................................................................................................... 20 5.3.1 MAC Search....................................................................................................................................... 20 5.3.2 Learning ............................................................................................................................................. 20 5.3.3 Aging .................................................................................................................................................. 20 5.4 Quality of Service ........................................................................................................................................ 20 5.5 Priority Classification Rule........................................................................................................................... 21 5.6 Port Based VLAN ........................................................................................................................................ 22 5.7 Memory Configurations ............................................................................................................................... 22
6.0 Frame Engine......................................................................................................................26
6.1 Data Forwarding Summary.......................................................................................................................... 26 6.2 Frame Engine Details .................................................................................................................................. 26 6.2.1 FCB Manager..................................................................................................................................... 26 6.2.2 Rx Interface........................................................................................................................................ 26 6.2.3 RxDMA............................................................................................................................................... 26 6.2.4 TxQ Manager ..................................................................................................................................... 26 6.3 Port Control ................................................................................................................................................. 27
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Data Sheet
6.4 TxDMA .........................................................................................................................................................27
7.0 Quality of Service and Flow Control ................................................................................ 27
7.1 Model ........................................................................................................................................................... 27 7.2 Four QoS Configurations .............................................................................................................................28 7.3 Delay Bound ................................................................................................................................................29 7.4 Strict Priority and Best Effort........................................................................................................................29 7.5 Weighted Fair Queuing ................................................................................................................................30 7.6 Shaper .........................................................................................................................................................30 7.7 WRED Drop Threshold Management Support.............................................................................................31 7.8 Buffer Management .....................................................................................................................................31 7.8.1 Dropping When Buffers Are Scarce ...................................................................................................32 7.9 MVTX2603 Flow Control Basics ..................................................................................................................33 7.9.1 Unicast Flow Control ..........................................................................................................................33 7.9.2 Multicast Flow Control ........................................................................................................................33 7.10 Mapping to IETF Diffserv Classes .............................................................................................................34
8.0 Port Trunking ..................................................................................................................... 35
8.1 Features and Restrictions ............................................................................................................................35 8.2 Unicast Packet Forwarding ..........................................................................................................................35 8.3 Multicast Packet Forwarding........................................................................................................................35 8.4 Trunking .......................................................................................................................................................36
9.0 Port Mirroring..................................................................................................................... 36
9.1 Port Mirroring Features ................................................................................................................................36 9.2 Setting Registers for Port Mirroring..............................................................................................................36
10.0 TBI Interface ..................................................................................................................... 37 11.0 GPSI (7WS) Interface ....................................................................................................... 38
11.1 11.1GPSI Connection ................................................................................................................................38 11.2 SCAN LINK and SCAN COL interface.......................................................................................................39
12.0 LED Interface.................................................................................................................... 39
12.1 LED Interface Introduction .........................................................................................................................39 12.2 Port Status .................................................................................................................................................39 12.3 LED Interface Timing Diagram...................................................................................................................40
13.0 Register Definition........................................................................................................... 41
13.1 MVTX2603 Register Description................................................................................................................41 13.2 Group 0 Address MAC Ports Group ..........................................................................................................44 13.2.1 ECR1Pn: Port N Control Register ....................................................................................................44 13.2.2 ECR2Pn: Port N Control Register ....................................................................................................45 13.2.3 GGControl - Extra GIGA Port Control..............................................................................................46 13.3 Group 1 Address VLAN Group ..................................................................................................................47 13.3.1 AVTCL - VLAN Type Code Register Low........................................................................................47 13.3.2 AVTCH - VLAN Type Code Register High ......................................................................................47 13.3.3 PVMAP00_0 - Port 00 Configuration Register 0 ............................................................................. 47 13.3.4 PVMAP00_1 - Port 00 Configuration Register 1 ............................................................................. 47 13.3.5 PVMAP00_2 - Port 00 Configuration Register 2 ............................................................................. 47 13.3.6 PVMAP00_3 - Port 00 Configuration Register 3 ............................................................................. 47 13.4 Port Configuration Register........................................................................................................................48 13.4.1 PVMODE..........................................................................................................................................49 13.4.2 TRUNK0_MODE- Trunk group 0 mode...........................................................................................49 13.4.3 TRUNK1_MODE - Trunk group 1 mode..........................................................................................50 13.5 Group 4 Address Search Engine Group ....................................................................................................50
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MVTX2603 Table of Contents
13.5.1 TX_AGE - Tx Queue Aging timer .................................................................................................... 50 13.5.2 AGETIME_LOW - MAC address aging time Low............................................................................ 50 13.5.3 AGETIME_HIGH -MAC address aging time High ........................................................................... 51 13.5.4 SE_OPMODE - Search Engine Operation Mode ............................................................................ 51 13.6 Group 5 Address Buffer Control/QOS Group ............................................................................................ 51 13.6.1 FCBAT - FCB Aging Timer.............................................................................................................. 51 13.6.2 QOSC - QOS Control ...................................................................................................................... 51 13.6.3 FCR - Flooding Control Register ..................................................................................................... 52 13.6.4 AVPML - VLAN Priority Map ........................................................................................................... 53 13.6.5 AVPMM - VLAN Priority Map .......................................................................................................... 53 13.6.6 AVPMH - VLAN Priority Map........................................................................................................... 53 13.6.7 TOSPML - TOS Priority Map........................................................................................................... 54 13.6.8 TOSPMM - TOS Priority Map.......................................................................................................... 54 13.6.9 TOSPMH - TOS Priority Map .......................................................................................................... 54 13.6.10 AVDM - VLAN Discard Map .......................................................................................................... 55 13.6.11 TOSDML - TOS Discard Map........................................................................................................ 55 13.6.12 BMRC - Broadcast/Multicast Rate Control..................................................................................... 56 13.6.13 UCC - Unicast Congestion Control................................................................................................ 56 13.6.14 MCC - Multicast Congestion Control ............................................................................................. 56 13.6.15 PR100 - Port Reservation for 10/100 ports ................................................................................... 57 13.6.16 PRG - Port Reservation for Giga ports.......................................................................................... 57 13.6.17 SFCB - Share FCB Size................................................................................................................ 58 13.6.18 C2RS - Class 2 Reserve Size ....................................................................................................... 58 13.6.19 C3RS - Class 3 Reserve Size ....................................................................................................... 58 13.6.20 C4RS - Class 4 Reserve Size ....................................................................................................... 58 13.6.21 C5RS - Class 5 Reserve Size ....................................................................................................... 58 13.6.22 C6RS - Class 6 Reserve Size ....................................................................................................... 59 13.6.23 C7RS - Class 7 Reserve Size ....................................................................................................... 59 13.6.24 Classes Byte Limit Set 0 ................................................................................................................ 59 13.6.25 Classes Byte Limit Set 1 ................................................................................................................ 59 13.6.26 Classes Byte Limit Set 2 ................................................................................................................ 60 13.6.27 Classes Byte Limit Set 3 ................................................................................................................ 60 13.6.28 Classes Byte Limit Giga Port 1 ...................................................................................................... 60 13.6.29 Classes Byte Limit Giga Port 2 ...................................................................................................... 61 13.6.30 Classes WFQ Credit Set 0 ............................................................................................................. 61 13.6.31 Classes WFQ Credit Set 1 ............................................................................................................. 61 13.6.32 Classes WFQ Credit Set 2 ............................................................................................................. 62 13.6.33 Classes WFQ Credit Set 3 ............................................................................................................. 62 13.6.34 Classes WFQ Credit Port G1 ......................................................................................................... 62 13.6.35 Classes WFQ Credit Port G2 ......................................................................................................... 63 13.6.36 Class 6 Shaper Control Port G1..................................................................................................... 63 13.6.37 Class 6 Shaper Control Port G2..................................................................................................... 63 13.6.38 RDRC0 - WRED Rate Control 0.................................................................................................... 64 13.6.39 RDRC1 - WRED Rate Control 1.................................................................................................... 64 13.6.40 User Defined Logical Ports and Well Known Ports ........................................................................ 64 13.6.40.1 USER_PORT0_(0~7) - User Define Logical Port (0~7)....................................................... 65 13.6.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority ........................... 65 13.6.40.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority ........................... 65 13.6.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority ........................... 66 13.6.40.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority ........................... 66 13.6.40.6 USER_PORT_ENABLE [7:0] - User Define Logic 7 to 0 Port Enables ............................... 66 13.6.40.7 WELL_KNOWN_PORT [1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority .............. 66
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Data Sheet
13.6.40.8 WELL_KNOWN_PORT [3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority...............66 13.6.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority...............67 13.6.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority.............67 13.6.40.11 WELL KNOWN_PORT_ENABLE [7:0] - Well Known Logic 7 to 0 Port Enables ...............67 13.6.40.12 RLOWL - User Define Range Low Bit 7:0..........................................................................67 13.6.40.13 RLOWH - User Define Range Low Bit 15:8 .......................................................................67 13.6.40.14 RHIGHL - User Define Range High Bit 7:0 ........................................................................67 13.6.40.15 RHIGHH - User Define Range High Bit 15:8 .....................................................................68 13.6.40.16 RPRIORITY - User Define Range Priority .........................................................................68 13.7 Group 6 Address MISC Group...................................................................................................................68 13.7.1 MII_OP0 - MII Register Option 0 .....................................................................................................68 13.7.2 MII_OP1 - MII Register Option 1 .....................................................................................................69 13.7.3 FEN - Feature Register ...................................................................................................................69 13.7.4 MIIC0 - MII Command Register 0....................................................................................................69 13.7.5 MIIC1 - MII Command Register 1....................................................................................................69 13.7.6 MIIC2 - MII Command Register 2....................................................................................................70 13.7.7 MIIC3 - MII Command Register 3....................................................................................................70 13.7.8 MIID0 - MII Data Register 0.............................................................................................................70 13.7.9 MIID1 - MII Data Register 1.............................................................................................................70 13.7.10 LED Mode - LED Control...............................................................................................................70 13.7.11 CHECKSUM - EEPROM Checksum ..............................................................................................71 13.8 Group 7 Address Port Mirroring Group .....................................................................................................71 13.8.1 MIRROR1_SRC - Port Mirror source port .......................................................................................71 13.8.2 MIRROR1_DEST - Port Mirror destination......................................................................................72 13.8.3 MIRROR2_SRC - Port Mirror source port .......................................................................................72 13.8.4 MIRROR2_DEST - Port Mirror destination......................................................................................72 13.9 Group F Address CPU Access Group .......................................................................................................72 13.9.1 GCR-Global Control Register...........................................................................................................72 13.9.2 DCR-Device Status and Signature Register ....................................................................................73 13.9.3 DCR1-Giga port status .....................................................................................................................73 13.9.4 DPST - Device Port Status Register................................................................................................74 13.9.5 DTST - Data read back register.......................................................................................................75 13.9.6 PLLCR - PLL Control Register .........................................................................................................75 13.9.7 LCLK - LA_CLK delay from internal OE_CLK .................................................................................75 13.9.8 OECLK - Internal OE_CLK delay from SCLK...................................................................................76 13.9.9 DA - DA Register .............................................................................................................................76 13.10 TBI Registers ...........................................................................................................................................76 13.10.1 Control Register .............................................................................................................................76 13.10.2 Status Register...............................................................................................................................77 13.10.3 Advertisement Register ..................................................................................................................77 13.10.4 Link Partner Ability Register ...........................................................................................................78 13.10.5 Expansion Register ........................................................................................................................78 13.10.6 Extended Status Register...............................................................................................................79
14.0 BGA and Ball Signal Descriptions ................................................................................. 80
14.1 BGA Views (Top-View) ..............................................................................................................................80 14.1.1 Encapsulated View...........................................................................................................................80 14.1.2 Power and Ground Distribution ........................................................................................................81 14.2 Ball - Signal Descriptions ..........................................................................................................................82 14.2.1 Ball Signal Descriptions....................................................................................................................82 14.3 Ball - Signal Name ....................................................................................................................................90 14.4 AC/DC Timing ............................................................................................................................................97 14.4.1 Absolute Maximum Ratings..............................................................................................................97
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MVTX2603 Table of Contents
14.4.2 DC Electrical Characteristics............................................................................................................ 97 14.4.3 Recommended Operation Conditions .............................................................................................. 97 14.5 Local Frame Buffer SBRAM Memory Interface ......................................................................................... 98 14.5.1 Local SBRAM Memory Interface...................................................................................................... 98 14.6 Local Switch Database SBRAM Memory Interface ................................................................................... 99 14.6.1 Local SBRAM Memory Interface:..................................................................................................... 99 14.7 AC Characteristics................................................................................................................................... 101 14.7.1 Reduced Media Independent Interface .......................................................................................... 101 14.7.2 LED Interface ................................................................................................................................. 106 14.7.3 SCANLINK SCANCOL Output Delay Timing ................................................................................. 106 14.7.4 MDIO Input Setup and Hold Timing ............................................................................................... 107 14.7.5 I2C Input Setup Timing .................................................................................................................. 108 14.7.6 Serial Interface Setup Timing......................................................................................................... 109
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MVTX2603 List of Figures
Figure 1 - MVTX2603 System Block Diagram ......................................................................................................... 1 Figure 2 - Data Transfer Format for I2C Interface.................................................................................................. 14 Figure 3 - Write Command..................................................................................................................................... 16 Figure 4 - Read Command .................................................................................................................................... 16 Figure 5 - MVTX2603 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only)........................................ 18 Figure 6 - Memory Map.......................................................................................................................................... 19 Figure 7 - Priority Classification Rule ..................................................................................................................... 21 Figure 8 - Memory Configuration For: 2 banks, 1 layer, 2MB total ........................................................................ 23 Figure 9 - Memory Configuration For: 2 banks, 2 Layer, 4MB total ....................................................................... 24 Figure 10 - Memory Configuration For: 2 banks, 1 layer, 4MB .............................................................................. 24 Figure 11 - Memory Configuration For: 2 banks, 2 layers, 4MB total..................................................................... 25 Figure 12 - Memory Configuration For: 2 banks, 1 layer, 4MB .............................................................................. 25 Figure 13 - Buffer Partition Scheme Used to Implement MVTX2603 Buffer Management .................................... 32 Figure 14 - TBI Connection .................................................................................................................................... 37 Figure 15 - GPSI (7WS) mode connection diagram............................................................................................... 38 Figure 16 - SCAN LINK and SCAN COLLISON status diagram ............................................................................ 39 Figure 17 - Timing Diagram of LED Interface ........................................................................................................ 40 Figure 18 - BGA View ............................................................................................................................................ 80 Figure 19 - Power and Ground Distribution View................................................................................................... 81 Figure 20 - Local Memory Interface - Input setup and hold timing ........................................................................ 98 Figure 21 - Local Memory Interface - Output valid delay timing............................................................................. 98 Figure 22 - Local Memory Interface - Input setup and hold timing ........................................................................ 99 Figure 23 - Local Memory Interface - Output valid delay timing........................................................................... 100 Figure 24 - AC Characteristics - Reduced Media Independent Interface............................................................ 101 Figure 25 - AC Characteristics - Reduced Media Independent Interface............................................................ 101 Figure 26 - AC Characteristics- GMII ................................................................................................................... 102 Figure 27 - AC Characteristics - Gigabit Media Independent Interface............................................................... 102 Figure 28 - AC Characteristics - Gigabit Media Independent Interface............................................................... 102 Figure 29 - Gigabit TBI Interface Transmit Timing ............................................................................................... 103 Figure 30 - Gigabit TBI Interface Receive Timing ................................................................................................ 103 Figure 31 - AC Characteristics- GMII ................................................................................................................... 104 Figure 32 - AC Characteristics - Gigabit Media Independent Interface............................................................... 104 Figure 33 - Gigabit TBI Interface Transmit Timing ............................................................................................... 105 Figure 34 - Gigabit TBI Interface Timing.............................................................................................................. 105 Figure 35 - AC Characteristics - LED Interface ................................................................................................... 106 Figure 36 - SCANLINK SCANCOL Output Delay Timing..................................................................................... 106 Figure 37 - SCANLINK, SCANCOL Setup Timing ............................................................................................... 106 Figure 38 - MDIO Input Setup and Hold Timing................................................................................................... 107 Figure 39 - MDIO Output Delay Timing ............................................................................................................... 107 Figure 40 - I2C Input Setup Timing ...................................................................................................................... 108 Figure 41 - I2C Output Delay Timing ................................................................................................................... 108 Figure 42 - Serial Interface Setup Timing ............................................................................................................ 109 Figure 43 - Serial Interface Output Delay Timing................................................................................................. 109
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MVTX2603 List of Tables
Table 1 - Memory Configuration .............................................................................................................................19 Table 2 - PVMAP Register ......................................................................................................................................22 Table 3 - Supported Memory Configurations (Pipeline SBRAM Mode) ..................................................................22 Table 4 - Supported Memory Configurations (ZBT Mode) ......................................................................................23 Table 5 - Options for Memory Configuration...........................................................................................................23 Table 6 - Two-dimensional World Traffic ................................................................................................................27 Table 7 - Four QoS Configurations for a 10/100 Mbps Port ...................................................................................28 Table 8 - Four QoS Configurations for a Gigabit Port .............................................................................................29 Table 9 - WRED Drop Thresholds ..........................................................................................................................31 Table 10 - Mapping between MVTX2603 and IETF Diffserv Classes for Gigabit Ports..........................................34 Table 11 - Mapping between MVTX2603 and IETF Diffserv Classes for 10/100 Ports ..........................................34 Table 12 - MVTX2603 Features Enabling IETF Diffserv Standards .......................................................................34 Table 13 - AC Characteristics - Local frame buffer SBRAM Memory Interface ....................................................99 Table 14 - AC Characteristics - Local Switch Database SBRAM Memory Interface............................................100 Table 15 - AC Characteristics - Reduced Media Independent Interface ..............................................................101 Table 16 - Output Delay Timing ............................................................................................................................103 Table 17 - Input Setup Timing...............................................................................................................................103 Table 18 - AC Characteristics - Gigabit Media Independent Interface .................................................................104 Table 19 - Output Delay Timing ............................................................................................................................105 Table 20 - Input Setup Timing...............................................................................................................................105 Table 21 - AC Characteristics - LED Interface .....................................................................................................106 Table 22 - SCANLINK, SCANCOL Timing............................................................................................................107 Table 23 - MDIO Timing........................................................................................................................................107 Table 24 - I2C Timing ...........................................................................................................................................108 Table 25 - Serial Interface Timing .........................................................................................................................109
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Data Sheet 1.0
1.1
MVTX2603
Block Functionality
Frame Data Buffer (FDB) Interfaces
The FDB interface supports pipelined synchronrous burst SRAM (SBRAM) memory at 100 MHz. To ensure a non-blocking switch, two memory domains are required. Each domain has a 64 bit wide memory bus. At 100 MHz, the aggregate memory bandwidth is 12.8 Gbps, which is enough to support 24 10/100 Mbps and 2 Gigabit ports at full wire speed switching. For 24+ 2 stacking application, ZBT memory at 125 MHz is required. The Switching Database is also located in the external SBRAM; it is used for storing MAC addresses and their physical port number. It is duplicated and stored in both memory domains. Therefore, when the system updates the contents of the switching database, it has to write the entry to both domains at the same time.
1.2
GMII/PCS MAC Module (GMAC)
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The MVTX2603 GMAC implements both GMII and MII interfaces, which offers a simple migration from 10/100 to 1G. The GMAC of the MVTX2603 meets the IEEE 802.3Z specification. It is able to operate in 10M/100M either Half or Full Duplex mode with a back pressure/flow control mechanism or in 1G full duplex mode with flow control mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. PHY addresses for GMAC are 01h and 02h.
1.3
Physical Coding Sublayer (PCI) Interface
For the MVTX2603, the 1000BASE-X PCI Interface is designed internally and may be utilized in the absence of a GMII. The PCS incorporates all the functions required by the GMII to include encoding (decoding) 8B GMII data to (from) 8B/10B TBI format for PHY communication and generating Collision Detect (COL) signals for half-duplex mode. It also manages the Auto negotiation process by informing the management entity that the PHY is ready for communications. The on-chip TBI may be disabled if TBI exists within the Gigabit PHY. The TBI interface provides a uniform interface for all 1000 Mbps PHY implementations. The PCS comprises the PCS Transmit, Synchronization, PCS Receive, and Auto negotiation processes for 1000BASE-X. The PCS Transmit process sends the TBI signals TXD [9:0] to the physical medium and generates the GMII Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission. Additionally, the Transmit process generates an internal "transmitting" flag and monitors Auto negotiation to determine whether to transmit data or to reconfigure the link. The PCS Synchronization process determines whether or not the receive channel is operational. The PCS Receive process generates RXD [7:0] on the GMII from the TBI data [9:0], and the internal "receiving" flag for use by the Transmit processes. The PCS Auto negotiation process allows the MVTX2603 to exchange configuration information between two devices that share a link segment, and to automatically configure the link for the appropriate speed of operation for both devices.
1.4
10/100 MAC Module (RMAC)
The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The MVTX2603 has two interfaces, RMII or Serial (only for 10M). The 10/100 MAC of the MVTX2603 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. The PHY address for 24 10/100 MAC are from 08h to 1fh.
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1.5 Configuration Interface Module
Data Sheet
The MVTX2603 supports a serial and an I2C interface, which provides an easy way to configure the system. Once configured, the resulting configuration can be stored in an I2C EEPROM.
1.6
Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent to the search engine, to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.7
Search Engine
The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2). It also performs MAC learning, priority assignment, and trunking functions.
1.8
LED Interface
The LED interface provides a serial interface for carrying 24+2 port status signals. It can also provide direct status pins (6) for the two Gigabit ports.
1.9
Internal Memory
Several internal tables are required and are described as follows: Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame stored in the FDB, e.g. frame size, read/write pointer, transmission priority, etc. * MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. The external MAC table is located in the FDB Memory. Note: the external MAC table is located in the external SBRAM Memory. *
2.0
2.1
System Configuration
Configuration Mode
The MVTX2603 can be configured by EEPROM (24C02 or compatible) via an I2C interface at boot time, or via a synchronous serial interface during operation.
2.2
I2C Interface
The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure 2 depicts the data transfer format.
START SLAVE ADDRESS R/W ACK DATA 1 (8 bits) ACK DATA 2 ACK DATA M ACK STOP
Figure 2 - Data Transfer Format for
I 2C
Interface
2.2.1
Start Condition
Generated by the master (in our case, the MVTX2603). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is free, both lines are High.
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Data Sheet
2.2.2 Address
MVTX2603
The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address.
2.2.3
Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R.
2.2.4
Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition.
2.2.5
Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB first.
2.2.6
Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line. The I2C interface serves the function of configuring the MVTX2603 at boot time. The master is the MVTX2603, and the slave is the EEPROM memory.
2.3
Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2603 not at boot time but via a PC. The PC serves as master and the MVTX2603 serves as slave. The protocol for the synchronous serial interface is nearly identical to the I2C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. The unmanaged MVTX2603 uses a synchronous serial interface to program the internal registers. To reduce the number of signals required, the register address, command and data are shifted in serially through the D0 pin. STROBE- pin is used as the shift clock. AUTOFD- pin is used as data return path. Each command consists of four parts. START pulse Register Address Read or Write command Data to be written or read back Any command can be aborted in the middle by sending a ABORT pulse to the MVTX2603. A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when STROBE- fall.
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MVTX2603
Data Sheet
An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when STROBE- fall.
2.3.1
Write Command
STROBE2 extra clock cycles 2 Extra clocks after last after transfer last transfer
D0
A2 A0 A1 A2 START
... A9 A10 A11 ... A9 A10 A11 W
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
ADDRESS
COMMAND
DATA
Figure 3 - Write Command
2.3.2
Read Command
STROBE-
D0
A0 A1 A2 ... A9 A10 A11 R A0 A1 A2 ... A9 A10 A11 R START ADDRESS COMMAND DATA
AUTOFD-
D0 D1 D2 D3 D4 D5 D6 D7 D5
Figure 4 - Read Command All registers in MVTX2603 can be modified through this synchronous serial interface.
2.4
Stacking
The two Gigabits ports can be used as link between boxes. Each Gigabit port can be accelerated to 2 Gpbs if desired (in conjunction with ZBT memory domains at 125MHz). If both Gigabit ports are used for this purpose, this provides a total of 4 Gbps of bandwidth between devices.
3.0
3.1
MVTX2603 Data Forwarding Protocol
Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. The memory (SRAM) interface consists of two 64-bit buses, connected to two SRAM banks, A and B. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn," the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
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Data Sheet
MVTX2603
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-port-per-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 4 transmission classes for each of the 24 10/100 ports, and 8 classes for each of the two Gigabit ports - a total of 112 unicast queues. The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line.
3.2
Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 2 multicast queues for each of the 24 10/100 ports. The queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entries. There are 4 multicast queues for each of the two Gigabit ports. The sizes of the queues are: 32 entries (higher priority queue, 32 entries, 32 entries and 64 entries (lower priority queue). There is one multicast queue for every two priority classes. For the 10/100 ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the gigabit ports to map the 8 transmit priorities into 4 multicast queues, the LSB are discarded. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined.
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MVTX2603
4.0
4.1
Data Sheet
Memory Interface
Overview
The MVTX2603 provides two 64-bit wide SRAM banks, SRAM Bank A and SRAM Bank B, with a 64-bit bus connected to each. Each DMA can read and write from both bank A and bank B. The following figure provides an overview of the MVTX2603 SRAM banks.
SRAM Bank A
SRAM Bank B
TXDMA 0-7
TXDMA 8-15
TXDMA 16-23
RXDMA 0-7
RXDMA 8-15
RXDMA 16-23
Figure 5 - MVTX2603 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only)
4.2
ZBT Support
The MVTX2603 supports Zero Bus Turnaround (ZBT). ZBT is a synchronous SRAM architecture that is optimized for networking and telecommunications applications. It can significantly increase the switch's internal bandwidth when compared to standard Pipeline SyncBurst SRAM. The ZBT architecture is optimized for switching and other applications with highly random READs and WRITEs. ZBT SRAMs eliminate all idle cycles when turning the data bus around from a WRITE operation to a READ operation (or vice versa). This feature results in dramatic performance improvements in systems that have such traffic patterns (that is, frequent and random read and write access to the SRAM). Please refer to the ZBT Application note for further details.
4.3
Detailed Memory Information
Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B, and so on in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then from B, and so on. The reading and writing from alternating memory banks can be performed with minimal waste of memory bandwidth. What's the worst case? For any speed port, in the worst case, a 1-byte-long EOF granule gets written to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next 8byte segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A, not B. This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the interframe gap is 20 bytes. Search engine data is written to both banks in parallel. In this way, a search engine read operation can be performed by either bank at any time without a problem.
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Data Sheet
4.4 Memory Requirements
MVTX2603
To speed up searching and decrease memory latency, the external MCT database is duplicated in both memory banks. To support 64K MCT, 4 MB memory is required. Up to 2K frame buffers are supported and they will use 3 MB of memory. The maximum system memory requirement is 4 MB. If less memory is desired, the configuration can scale down proportionally. Bank A 1M 2M 1M 2M Bank B 1K 2K Table 1 - Memory Configuration
1M Bank A 0.75M 0.25M 1M Bank B 0.75M 0.25M 2M Bank A 1.5M 0.5M 2M Bank B 1.5M 0.5M
Frame Buffer
Max MAC Address 32K 64k
Frame Data Buffer (FDR) Area MAC Address Control Table (MCT) Area
Figure 6 - Memory Map
5.0
5.1
Search Engine
Search Engine Overview
The MVTX2603 search engine is optimized for high throughput searching, with enhanced features to support: * * * * * * Up to 64K MAC addresses 3 groups of port trunking (1 for the two Gigabit ports, and 2 others) Traffic classification into 4 (or 8 for Gigabit) transmission priorities, and 2 drop precedence levels Flooding, Broadcast, Multicast Storm Control MAC address learning and aging Port based VLAN
5.2
Basic Flow
Shortly after a frame enters the MVTX2603 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, the transmission and discard priorities, whether the frame is unicast or multicast. Requests are sent to the external SRAM to locate the associated entries in the external hash table.
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MVTX2603
Data Sheet
When all the information has been collected from external SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). In addition, port based VLAN information is used to select the correct set of destination ports for the frame (for multicast), or to verify that the frame's destination port is associated with the VLAN (for unicast). If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. When all the information is compiled, the switch response is generated, as stated earlier.
5.3 5.3.1
Search, Learning, and Aging MAC Search
The search block performs source MAC address and destination MAC address searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. The port based VLAN bitmap is used to determine whether the frame should be forwarded to the outgoing port. When the egress port is not included in the ingress port VLAN bitmap, the packet is discarded. The MAC search block is also responsible for updating the source MAC address timestamp and the VLAN port association timestamp, used for aging.
5.3.2
Learning
The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. Learning and port change will be performed based on memory slot availability only.
5.3.3
Aging
Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table.
5.4
Quality of Service
Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate traffic, a service level known as "best effort" attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. In a congested network or when a low-performance switch/router is overloaded, "best effort" becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously plagued such "best effort" networking systems. QoS provides Ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth.
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Data Sheet
MVTX2603
Extensive core QoS mechanisms are built into the MVTX2603 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the MVTX2603, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. For example, the overall service given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay. The MVTX2603 supports the following QoS techniques: * * * In a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority. In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be mapped to different queues in the switch to provide QoS. In a TOS/DS-based set up, TOS stands for "Type of Service" that may include "minimize delay," "maximize throughput," or "maximize reliability." Network nodes may select routing paths or forwarding behaviours that are suitably engineered to satisfy the service request. In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as VoIP.
*
5.5
Priority Classification Rule
Figure 7 on page 21 shows the MVTX2603 priority classification rule
Yes Fix Port Priority ? No Use Default Port Settings No IP Yes No TOS Precedence over VLAN? (FCR Register, Bit 7) No VLAN Tag ? No IP Frame ? Yes Use Default Port Settings
Yes
Yes Use Logical Port Yes No
Use TOS
Use VLAN Priority
Use Logical Port
Figure 7 - Priority Classification Rule
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MVTX2603
5.6 Port Based VLAN
Data Sheet
An administrator can use the PVMAP Registers to configure the MVTX2603 for port-based VLAN. For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The MVTX2603 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the MVTX2603 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. Destination Port Numbers Bit Map Port Registers Register for Port #0 PVMAP00_0[7:0] to PVMAP00_3[2:0] Register for Port #1 PVMAP01_0[7:0] to PVMAP01_3[2:0] Register for Port #2 PVMAP02_0[7:0] to PVMAP02_3[2:0] ... Register for Port #26 PVMAP26_0[7:0] to PVMAP26_3[2:0] 0 0 0 0 26 0 0 0 ... 2 1 1 0 1 1 0 0 0 0 1 0
Table 2 - PVMAP Register For example, in the above table, a 1 denotes that an outgoing port is eligible to receive a packet from an incoming port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. In this example * * * Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2 Data packets received at port #1 are eligible to be sent to outgoing ports 0, and 2 Data packets received at port #2 are not eligible to be sent to ports 0 and 1
5.7
Memory Configurations
The MVTX2603 supports the following memory configurations. SBRAM modes support 1M and 2M configurations, while ZBT mode supports 4M configurations, 2M per domain (bank). For detail connection information, please reference the memory application note. 1 M per bank (Bootstrap pin TSTOUT7 = open) Two 128K x 32 SRAM/bank or
One 128 K x 64 SRAM/bank
Configuration Single Layer (Bootstrap pin TSTOUT13 = open) Double Layer (Bootstrap pin TSTOUT13 = pull down)
2 M per bank (Bootstrap pin TSTOUT7 = pull down) Two 256K x 32 SRAM/bank Four 128K x 32 SRAM/bank or
Two 128 K x 64 SRAM/bank
Connections Connect 0E# and WE#
NA
Connect 0E0# and WE0# Connect 0E1# and WE1#
Table 3 - Supported Memory Configurations (Pipeline SBRAM Mode)
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Data Sheet
MVTX2603
2 M per bank Two 256 K x 32 ZBT SRAM/bank or One 256 K x 64 ZBT SRAM/bank Four 128 K x 32 ZBT SRAM/bank or Two 128 K x 64 ZBT SRAM/bank Connections Connect ADS# to Layer 0 chipselect pin Connect ADS# to Layer 0 chipselect pin and 0E# to Layer 1 chipselect pin
Configuration Single Layer (Bootstrap pin TSTOUT13 = open) Double Layer (Bootstrap pin TSTOUT13 = pull down)
Table 4 - Supported Memory Configurations (ZBT Mode) Frame data Buffer Only Bank A 1M (SRAM) MVTX2601 MVTX2602 MVTX2603 MVTX2603 (Gigabit ports in 2giga mode) MVTX2604 MVTX2604 (Gigabit ports in 2giga mode) Table 5 - Options for Memory Configuration
Bank A (1M One Layer)
Data LA_D[63:32]
Bank A and Bank B 1M/bank (SRAM) 2M/bank (SRAM)
Bank A and Bank B 1M/bank (ZBT SRAM) 2M/bank (ZBT SRAM)
2M (SRAM) X X
X X
X
X X (125Mhz) X (125Mhz)
X
X X (125Mhz) X (125Mhz)
Bank B (1M One Layer)
Data LB_D[63:32]
Data LA_D[31:0] SRAM Memory 128K 32 bits Memory 128K 32 bits
Data LB_D[31:0] SRAM Memory 128K 32 bits Memory 128K 32 bits
Address LA_A[19:3]
Address LB_A[19:3]
B
tt
TSTOUT7
O
Figure 8 - Memory Configuration For: 2 banks, 1 layer, 2MB total
TSTOUT13
O
TSTOUT4
O
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MVTX2603
BANK A (2M Two Layers)
Data LA_D[63:32] Data LA_D[31:0]
Data Sheet
BANK B (2M Two Layers)
Data LB_D[63:32]
SRAM Memory 128 K 32 bits
SRAM Memory 128 K 32 bits
Data LB_D[31:0]
SRAM Memory 128 K 32 bits
SRAM Memory 128 K 32 bits
SRAM Memory 128 K 32 bits
SRAM Memory 128 K 32 bits
SRAM Memory 128 K 32 bits
SRAM Memory 128 K 32 bits
Address LA_A[19:3]
Address LB_A[19:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open
M C fi ti F 2 b k 2 banks, 2 Layer, 4MB total 4MB t t l Figure 9 - Memory Configuration For: 2 L
BANK A (2M One Layer)
Data LA_D[63:32] Data LA_D[31:0]
BANK B (2M One Layer)
Data LB_D[63:32] Data LB_D[31:0]
SRAM Memory 256 K 32 bits
Memory 256 K 32 bits
SRAM Memory 256 K 32 bits
Memory 256 K 32 bits
Address LA_A[20:3]
Address LB_A[20:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open
Figure 10 - Memory Configuration For: 2 banks, 1 layer, 4MB
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Data Sheet
MVTX2603
BANK A (2M Two Layers)
Data LA_D[63:32]
BANK B (2M Two Layers)
Data LB_D[63:32]
Data LA_D[31:0]
ZBT Memory 128 K 32 bits
ZBT Memory 128 K 32 bits
Data LB_D[31:0]
ZBT Memory 128 K 32 bits
ZBT Memory 128 K 32 bits
ZBT Memory 128 K 32 bits
ZBT Memory 128 K 32 bits
ZBT Memory 128 K 32 bits
ZBT Memory 128 K 32 bits
Address LA_A[19:3]
Address LB_A[19:3]
Figure 11 - Memory Configuration For: 2 banks, 2 layers, 4MB total
BANK A (2M One Layer)
Data LA_D[63:32] Data LA_D[31:0]
BANK B (2M One Layer)
Data LB_D[63:32] Data LB_D[31:0]
ZBT Memory 256 K 32 bits
ZBT Memory 256 K 32 bits
ZBT Memory 256 K 32 bits
ZBT Memory 256 K 32 bits
Address LA_A[20:3]
Address LB_A[20:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Pull Down
Figure 12 - Memory Configuration For: 2 banks, 1 layer, 4MB
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MVTX2603
6.0
6.1
* * * *
Data Sheet
Frame Engine
Data Forwarding Summary
*
*
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface. A switch request is sent to the Search Engine. The Search Engine processes the switch request. A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast, and its destination port or ports. A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are 4 TxSch Q for each 10/100 port (and 8 per Gigabit port), one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of the TxSch Qs, according to the transmission scheduling algorithm (to ensure per-class quality of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older HOL between the two queues goes first. For 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. For Gigabit ports multicast queue 0 is associated with unicast queue 0, multicast queue 1 with unicast queue 2, multicast queue 2 with unicast queue 4 and multicast queue 3 with unicast queue 6. The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port.
6.2
Frame Engine Details
This section briefly describes the functions of each of the modules of the MVTX2603 frame engine.
6.2.1
FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register FCBAT.
6.2.2
Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch request.
6.2.3
RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made.
6.2.4
TxQ Manager
First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the TxQ manager requests that the FCB manager link the unicast frame's FCB to the correct per-port-perclass TxQ. If multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port control module.
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Data Sheet
6.3 Port Control
MVTX2603
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released.
6.4
TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules.
7.0
7.1
Quality of Service and Flow Control
Model
Quality of service is an all-encompassing term for which different people have different interpretations. In general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch's performance. Table 6 on page 27 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. Gigabit ports actually have eight total transmission priorities. Total
Goals Highest transmission priority, P3
Assured Bandwidth (user defined)
Low Drop Probability (low-drop) Apps: phone calls, circuit emulation. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed. Apps: interactive apps, Web business. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed. Apps: emails, file backups. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed.
High Drop Probability (high-drop) Apps: training video. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to drop otherwise. Apps: non-critical interactive apps. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed; firstP2 to drop otherwise. Apps: casual web browsing. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed; first to drop otherwise.
50 Mbps
Middle transmission priority, P2
37.5 Mbps
Low transmission priority, P1
12.5 Mbps
Total
100 Mbps Table 6 - Two-dimensional World Traffic
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MVTX2603
Data Sheet
A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the quality of service (QoS) received by well-behaved classes. As Table 6 illustrates, the six traffic types may each have their own distinct properties and applications. As shown, classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 Mbps of bandwidth at that port. Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the MVTX2603, each 10/100 Mbps port will support four total classes, and each 1000 Mbps port will support eight classes. We will discuss the various modes of scheduling these classes in the next section. In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely lose packets. But poorly behaved users - users who send frames at too high a rate - will encounter frame loss, and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. Table 6 shows that different types of applications may be placed in different boxes in the traffic table. For example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category of low-loss, low-latency traffic.
7.2
Four QoS Configurations
There are four basic pieces to QoS scheduling in the MVTX2603: strict priority (SP), delay bound, weighted fair queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as shown in Table 4, "Supported Memory Configurations (ZBT Mode)," and Table 6, "Two-dimensional World Traffic," . For 10/100 Mbps ports, these modes are selected by the following registers: QOSC24 [7:6] QOSC28 [7:6] QOSC32 [7:6] QOSC36 [7:6] P3 Op1 (default) Op2 Op3 Op4 Delay Bound SP SP WFQ Table 7 - Four QoS Configurations for a 10/100 Mbps Port Delay Bound WFQ CREDIT_C00 CREDIT_C10 CREDIT_C20 CREDIT_C30 P2 P1 BE BE P0
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Data Sheet
MVTX2603
These modes are selected by QOSC40 [7:6] and QOSC48 [7:6] for the first and second gigabit ports, respectively. P7 Op1 (default) Op2 Op3 Op4 Delay Bound SP SP WFQ Table 8 - Four QoS Configurations for a Gigabit Port The default configuration for a 10/100 Mbps port is three delay-bounded queues and one best-effort queue. The delay bounds per class are 0.8 ms for P3, 2 ms for P2, and 12.8 ms for P1. For a 1 Gbps port, we have a default of six delay-bounded queues and two best-effort queues. The delay bounds for a 1 Gbps port are 0.16 ms for P7 and P6, 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. Best effort traffic is only served when there is no delay-bounded traffic to be served. For a 1 Gbps port, where there are two best-effort queues, P1 has strict priority over P0. We have a second configuration for a 10/100 Mbps port in which there is one strict priority queue, two delay bounded queues, and one best effort queue. The delay bounds per class are 3.2 ms for P2 and 12.8 ms for P1. If the user is to choose this configuration, it is important that P3 (SP) traffic be either policed or implicitly bounded (e.g. if the incoming P3 traffic is very light and predictably patterned). Strict priority traffic, if not admission-controlled at a prior stage to the MVTX2603, can have an adverse effect on all other classes' performance. For a 1 Gbps port, P7 and P6 are both SP classes, and P7 has strict priority over P6. In this case, the delay bounds per class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. The third configuration for a 10/100 Mbps port contains one strict priority queue and three queues receiving a bandwidth partition via WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled. In the fourth configuration, all queues are served using a WFQ service discipline. Delay Bound WFQ P6 P5 P4 P3 P2 P1 BE BE P0
7.3
Delay Bound
In the absence of a sophisticated QoS server and signaling protocol, the MVTX2603 may not know the mix of incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL) frames. As a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. Our algorithm also differentiates between high-drop and lowdrop traffic with a weighted random early drop (WRED) approach. Random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip's buffers are completely full, while still largely sparing low-drop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. Finally, the delay bound algorithm also achieves bandwidth partitioning among classes.
7.4
Strict Priority and Best Effort
When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes. When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance. However, in a typical network setting, much best effort traffic will indeed be transmitted, and with an adequate degree of expediency.
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MVTX2603
Data Sheet
Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the MVTX2603, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best effort and strict priority queues when global buffer resources become scarce.
7.5
Weighted Fair Queuing
In some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, WFQ may be preferable to a delay-bounded scheduling discipline. The MVTX2603 provides the user with a WFQ option with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. The user sets four WFQ "weights" (eight for Gigabit ports) such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with error within 2%. In WFQ mode, though we do not assure frame latency, the MVTX2603 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do indeed drop frames from SP queues for global buffer management purposes. In addition, queue P0 for a 10/100 port (and queues P0 and P1 for a Gigabit port) are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping when the global buffer count becomes low.
7.6
Shaper
Although traffic shaping is not a primary function of the MVTX2603, the chip does implement a shaper for expedited forwarding (EF). Our goal in shaping is to control the peak and average rate of traffic exiting the MVTX2603. Shaping is limited to the two Gigabit ports only, and only to class P6 (the second highest priority). This means that class P6 will be the class used for EF traffic. If shaping is enabled for P6, then P6 traffic must be scheduled using strict priority. With reference to Table 8 only the middle two QoS configurations may be used. Peak rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then the peak rate for shaped traffic is 32/64 * 1000 Mbps = 500 Mbps. Average rate is also a programmable whole number, no greater than 64, and no greater than the peak rate. For example, if the setting is 16, then the average rate for shaped traffic is 16/64 * 1000 Mbps = 250 Mbps. As a consequence of the above settings in our example, shaped traffic will exit the MVTX2603 at a rate always less than 500 Mbps, and averaging no greater than 250 Mbps. See Programming QoS Registers application note for more information. Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. Though we do have global resource management, we do nothing to prevent this situation locally. We assume SP traffic is policed at a prior stage to the MVTX2603.
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Data Sheet
7.7 WRED Drop Threshold Management Support
MVTX2603
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic.
Table 9 - WRED Drop Thresholds Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds for each priority queue. They can be programmed by the QOS control register (refer to the register group 5.)
7.8
Buffer Management
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the MVTX2603. Our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in Figure 13 on page 32. As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the MVTX2603, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100 Mbps ports, a frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only four transmission scheduling queues for 10/100 Mbps ports, but as far as buffer usage is concerned, there are still eight distinguishable classes. Another segment of the FDB reserves space for each of the 26 ports ethernet port. Two parameters can be set, one for the source port reservation for 10/100 Mbps ports, and one for the source port reservation for 1 Gbps ports. These 26 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port.
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MVTX2603
The following registers define the size of each section of the frame data buffer: PR100- Port Reservation for 10/100 Ports PRG- Port Reservation for Giga Ports SFCB- Share FCB Size C2RS- Class 2 Reserve Size C3RS- Class 3 Reserve Size C4RS- Class 4 Reserve Size C5RS- Class 5 Reserve Size C6RS- Class 6 Reserve Size C7RS- Class 7 Reserve Size
Data Sheet
temporary reservation
shared pool S per-class reservation
per-source reservations (24 10/100M, CPU)
per-source reservations (2G)
Figure 13 - Buffer Partition Scheme Used to Implement MVTX2603 Buffer Management
7.8.1
Dropping When Buffers Are Scarce
Summarizing the two examples of local dropping discussed earlier in this chapter: * If a queue is a delay-bounded queue, we have a multi-level WRED drop scheme, designed to control delay and partition bandwidth in case of congestion. * If a queue is a WFQ-scheduled queue, we have a multi-level WRED drop scheme, designed to prevent congestion. In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer management is to make sure that such dropping causes as little blocking as possible.
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Data Sheet
7.9 MVTX2603 Flow Control Basics
MVTX2603
Because frame loss is unacceptable for some applications, the MVTX2603 provides a flow control option. When flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch, to temporarily hold off. While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. A single packet destined for a congested output can block other packets destined for uncongested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. In the MVTX2603, each source port can independently have flow control enabled or disabled. For flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priority. What this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible expense of minimum bandwidth or maximum delay assurances. In addition, these "downgraded" frames may only use the shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not use reserved FDB slots for the highest six classes (P2-P7). The MVTX2603 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for frames originating from flow control enabled ports. When this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. The reason is that intelligent packet dropping is a major component of the MVTX2603's approach to ensuring bounded delay and minimum bandwidth for high priority flows.
7.9.1
Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the MVTX2603's buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is triggered when a port is currently being flow controlled, and all of that port's reserved FDB slots have been released. Note that the MVTX2603's per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled.
7.9.2
Multicast Flow Control
In unmanaged mode, flow control for multicast frames is triggered by a global buffer counter. When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold. In managed mode, per-VLAN flow control is used for multicast frames. In this case, flow control is triggered by congestion at the destination. How so? The MVTX2603 checks each destination to which a multicast packet is headed. For each destination port, the occupancy of the lowest-priority transmission multicast queue (measured in number of frames) is compared against a programmable congestion threshold. If congestion is detected at even one of the packet's destinations, then Xoff is triggered. In addition, each source port has a 26-bit port map recording which port or ports of the multicast frame's fanout were congested at the time Xoff was triggered. All ports are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were originally marked as congested in the port map have become uncongested, then Xon is triggered, and the 26-bit vector is reset to zero. The MVTX2603 also provides the option of disabling VLAN multicast flow control.
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MVTX2603
Data Sheet
Note: If per-Port flow control is on, QoS performance will be affected. To determine the most efficient way to program, please refer to the QoS Application Note.
7.10
Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below. VTX IETF P7 NM P6 EF P5 AF0 P4 AF1 P3 AF2 P2 AF3 P1 BE0 P0 BE1
Table 10 - Mapping between MVTX2603 and IETF Diffserv Classes for Gigabit Ports As the table illustrates, P7 is used solely for network management (NM) frames. P6 is used for expedited forwarding service (EF). Classes P2 through P5 correspond to an assured forwarding (AF) group of size 4. Finally, P0 and P1 are two best effort (BE) classes. For 10/100 Mbps ports, the classes of Table 12 are merged in pairs--one class corresponding to NM+EF, two AF classes, and a single BE class. VTX IETF P3 NM+EF P2 AF0 P1 AF1 P0 BE0
Table 11 - Mapping between MVTX2603 and IETF Diffserv Classes for 10/100 Ports Features of the MVTX2603 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) * * * * * * * * * Best effort (BE) * * * * Global buffer reservation for NM and EF Shaper for EF traffic on 1 Gbps ports Option of strict priority scheduling No dropping if admission controlled Four AF classes for 1 Gbps ports Programmable bandwidth partition, with option of WFQ service Option of delay-bounded service keeps delay under fixed levels even if not admission-controlled Random early discard, with programmable levels Global buffer reservation for each AF class Two BE classes for 1 Gbps ports Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE
Assured forwarding (AF)
Table 12 - MVTX2603 Features Enabling IETF Diffserv Standards
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Data Sheet 8.0
8.1
MVTX2603
Port Trunking
Features and Restrictions
A port group (i.e. trunk) can include up to 4 physical ports, but all of the ports in a group must be in the same MVTX2603. The two Gigabit ports may also be trunked together. There are three trunk groups total, including the option to trunk Gigabit ports. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address. Three other options include source MAC address only, destination MAC address only, and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly. If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN member map. The MVTX2603 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the MVTX2603 will automatically redistribute the traffic over to the remaining ports in the trunk.
8.2
Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address belongs to a trunk, then the source port's trunk membership register is checked. A hash key, based on some combination of the source and destination MAC addresses for the current packet, selects the appropriate forwarding port.
8.3
Multicast Packet Forwarding
For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the VLAN index and hash key. Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. Determining one forwarding port per group. For multicast packets, all but one port per group, the forwarding port, must be excluded. Preventing the multicast packet from looping back to the source trunk. The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. This is because, when we select the primary forwarding port for each group, we do not take the source port into account. To prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet.
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MVTX2603
8.4 Trunking
Data Sheet
3 trunk groups are supported. Groups 0 and 1 can trunk up to 4 10/100 ports. Group 2 can trunk 2 Gigabit ports. The supported combinations are shown in the following table. Group 0 Port 0 X X X Select via trunk0_mode register Group 1 Port 4 X X Select via trunk1_mode register Group 2 Port 25(Giga 0) X The trunks are individually enabled/disabled by controlling pin trunk 0,1,2. Port 26 (Giga 1) X Port 5 X X X X Port 6 Port 7 Port 1 X X X X X X Port 2 Port 3
9.0
9.1
Port Mirroring
Port Mirroring Features
The received or transmitted data of any 10/100 port in the MVTX2603 chip can be "mirrored" to any other port. We support two such mirrored source-destination pairs. A mirror port cannot also serve as a data port. Please refer to the Port Mirroring Application note for further details.
9.2
*
Setting Registers for Port Mirroring
MIRROR1_SRC: Sets the source port for the first port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR1_DEST: Sets the destination port for the first port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 23. MIRROR2_SRC: Sets the source port for the second port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 0.
* *
*
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Data Sheet 10.0 TBI Interface
MVTX2603
The TBI interface can be used for 1000Mbps fiber operation. In this mode, the MVTX2603 is connected to the Serdes as shown in Figure 14. There are two TBI interfaces in the MVTX2603 devices. To enable to TBI function, the corresponding TXEN and TXER pins need to be boot strapped. See Ball - Signal Description for details.
M25/26_TXD[9:0] M25/26_TXCLK
T[9:0] REFCLK
MVTX2603
SERDES
M25/26_RXD[9:0] M25/26_RXCLK M25/26_COL
R[9:0] RBC0 RBC1
Figure 14 - TBI Connection
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MVTX2603
11.0
11.1
Data Sheet
GPSI (7WS) Interface
11.1GPSI Connection
The 10/100 RMII ethernet port can function in GPSI (7WS) mode when the corresponding TXEN pin is strapped low with a 1K pull down resistor. In this mode, the TXD[0], TXD[1], RXD[0] and RXD[1] serve as TX data, TX clock, RX data and RX clock respectively. The link status and collision from the PHY are multiplexed and shifted into the switch device through external glue logic. The duplex of the port can be controlled by programming the ECR register. The GPSI interface can be operated in port based VLAN mode only
CRS_DV RXD[0] RXD[1] TXD[1] TXD[0] TXEN
crs rxd rx_clk tx_clk txd txen Port 0 Ethernet PHY link0 col0
link1 260X link2
col1 col2
link23 col23 Port 23 Ethernet PHY
SCAN_LINK
SCAN_COL
SCAN_CLK
Link Serializer (CPLD)
Collision Serializer (CPLD)
Figure 15 - GPSI (7WS) mode connection diagram
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Data Sheet
11.2 SCAN LINK and SCAN COL interface
MVTX2603
An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYs and shift them into the switch device. The switch device will drive out a signature to indicate the start of the sequence. After that, the CPLD should shift in the link and collision status of the PHYS as shown in the figure. The extra link status indicates the polarity of the link signal. One indicates the polarity of the link signal is active high.
scan_clk scan_link/ scan_col
25 cycles for link/ 24 cycles for col Drived by VTX260x Driven by MVTX260x Drived by CPLD Driven by CPLD
Total cycles period Total 32 32 cycles period
Figure 16 - SCAN LINK and SCAN COLLISON status diagram
12.0
12.1
LED Interface
LED Interface Introduction
A serial output channel provides port status information from the MVTX2603 chips. It requires three additional pins: * * * A LED_CLK at 12.5 MHz LED_SYN a sync pulse that defines the boundary between status frames LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time non-serial interface is also allowed, but in this case, only the Gigabit ports will have status LEDs.
A low cost external device (44 pin PAL) is used to decode the serial data and to drive an LED array for display. This device can be customized for different needs.
12.2
Port Status
In the MVTX2603, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators are * Bit 0: Flow control * Bit 1:Transmit data * Bit 2: Receive data * Bit 3: Activity (where activity includes either transmission or reception of data) * Bit 4: Link up * Bit 5: Speed (1= 100 Mb/s; 0= 10 Mb/s) * Bit 6: Full-duplex * Bit 7: Collision Eight clocks are required to cycle through the eight status bits for each port.
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MVTX2603
Data Sheet
When the LED_SYN pulse is asserted, the LED interface will present 256 LED clock cycles with the clock cycles providing information for the following ports. Port 0 (10/100): cycles #0 to cycle #7 Port 1 (10/100): cycles#8 to cycle #15 Port 2 (10/100): cycle #16 to cycle #23 ... Port 22 (10/100): cycle #176 to cycle #183 Port 23 (10/100): cycle #184 to cycle #191 Port 24 (Gigabit 0): cycle #192 to cycle #199 Port 25 (Gigabit 1): cycle #200 to cycle #207 Byte 26 (additional status): cycle #208 to cycle #215 Byte 27 (additional status): cycle #216 to cycle #223 Cycles #224 to 256 present data with a value of zero. The first two bits of byte 26 provides the speed information for the Gigabit ports while the remainder of byte 26 and byte 27 provides bit status * * * * * * * * * * 26[0]: G0 port (1= port 24 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on speed bit of Port 24) 26[1]: G1 port (1= port 25 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on speed bit of Port 25) 26[2]: initialization done 26[3]: initialization start 26[4]: checksum ok 26[5]: link_init_complete 26[6]: bist_fail 26[7]: ram_error 27[0]: bist_in_process 27[1]: bist_done
12.3
LED Interface Timing Diagram
The signal from the MVTX2603 to the LED decoder is shown in Figure 17.
Figure 17 - Timing Diagram of LED Interface
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Data Sheet 13.0
13.1
MVTX2603
Register Definition
MVTX2603 Register Description
Register Description CPU Addr (Hex) R/W I2C Addr (Hex) Default Notes
0. ETHERNET Port Control Registers Substitute [N] with Port number (0..17h, 19h, 1Ah) ECR1P"N" ECR2P"N" Port Control Register 1 for Port N Port Control Register 2 for Port N 0000 + 2 x N 001 + 2 x N R/W R/W 000-018 01B-033 020 000
1. VLAN Control Registers Substitute [N] with Port number (0..17h, 19h, 1Ah) AVTCL AVTCH PVMAP"N"_0 PVMAP"N"_1 PVMAP"N"_2 PVMAP"N"_3 PVMODE VLAN Type Code Register Low VLAN Type Code Register High Port "N" Configuration Register 0 Port "N" Configuration Register 1 Port "N" Configuration Register 2 Port "N" Configuration Register 3 VLAN Operating Mode 100 101 102 + 4N 103 + 4N 104 + 4N 105 + 4N 170 R/W R/W R/W R/W R/W R/W R/W 036 037 038-052 053-06D 06E-088 089-0A3 0A4 000 081 0FF 0FF 0FF 007 000
2. TRUNK Control Registers TRUNK0_ MODE TRUNK1_ MODE TRUNK2_ MODE TX_AGE Trunk Group 0 Mode Trunk Group 1 Mode Trunk Group 2 Mode Transmission Queue Aging Time 203 20B 210 325 R/W R/W R/W R/W 0A5 0A6 NA 0A7 003 003 003 008
3. Search Engine Configurations AGETIME_LOW AGETIME_ HIGH SE_OPMODE MAC Address Aging Time Low MAC Address Aging Time High Search Engine Operating Mode 400 401 403 R/W R/W R/W 0A8 0A9 NA 2M:05C/ 4M:02E 000 000
4. Buffer Control and QOS Control FCBAT QOSC FCR AVPML AVPMM AVPMH TOSPML TOSPMM FCB Aging Timer QOS Control Flooding Control Register VLAN Priority Map Low VLAN Priority Map Middle VLAN Priority Map High TOS Priority Map Low TOS Priority Map Middle 500 501 502 503 504 505 506 507 R/W R/W R/W R/W R/W R/W R/W R/W 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0FF 000 008 000 000 000 000 000
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MVTX2603
Register TOSPMH AVDM TOSDML BMRC UCC MCC PR100 SFCB C2RS C3RS C4RS C5RS C6RS C7RS QOSC"N" RDRC0 RDRC1 USER_ PORT"N"_LOW USER_ PORT"N"_HIGH USER_ PORT1:0_ PRIORITY USER_ PORT3:2_ PRIORITY USER_ PORT5:4_ PRIORITY USER_ PORT7:6_PRI ORITY USER_PORT_ ENABLE WLPP10 WLPP32 Description TOS Priority Map High VLAN Discard Map TOS Discard Map Broadcast/Multicast Rate Control Unicast Congestion Control Multicast Congestion Control Port Reservation for 10/100 Ports Share FCB Size Class 2 Reserve Size Class 3 Reserve Size Class 4 Reserve Size Class 5 Reserve Size Class 6 Reserve Size Class 7 Reserve Size QOS Control (N=0 59) WRED Drop Rate Control 0 WRED Drop Rate Control 1 User Define Logical Port "N" Low (N=0-7) User Define Logical Port "N" High User Define Logic Port 1 and 0 Priority User Define Logic Port 3 and 2 Priority User Define Logic Port 5 and 4 Priority User Define Logic Port 7 and 6 Priority CPU Addr (Hex) 508 509 50A 50B 50C 50D 50E 510 511 512 513 514 515 516 517 512 553 554 580 + 2N 581 + 2N 590 591 592 593 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W I2C Addr (Hex) 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0BA 0BB 0BC 0BD 0BE 0BF 0C0 0C1-0D2 0FB 0FC 0D6-0DD 0DE-0E5 0E6 0E7 0E8 0E9
Data Sheet
Default 000 000 000 000 2M:008/ 4M:010 050 2M:024/ 4M:036 2M:014/ 4M:064 000 000 000 000 000 000 000 08F 088 000 000 000 000 000 000
Notes
User Define Logic Port Enable Well known Logic Port Priority for 1 and 0 Well known Logic Port Priority for 3 and 2
594 595 596
R/W R/W R/W
0EA 0EB 0EC
000 000 000
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Data Sheet
Register WLPP54 WLPP76 WLPE RLOWL RLOWH RHIGHL RHIGHH RPRIORITY Description Well known Logic Port Priority for 5 and 4 Well-known Logic Port Priority for 7 & 6 Well known Logic Port Enable User Define Range Low Bit7:0 User Define Range Low Bit 15:8 User Define Range High Bit 7:0 User Define Range High Bit 15:8 User Define Range Priority CPU Addr (Hex) 597 598 599 59A 59B 59C 59D 59E R/W R/W R/W R/W R/W R/W R/W R/W R/W I2C Addr (Hex) 0ED 0EE 0EF 0F4 0F5 0D3 0D4 0D5
MVTX2603
Default 000 000 000 000 000 000 000 000 Notes
5. MISC Configuration Registers MII_OP0 MII_OP1 FEN MIIC0 MIIC1 MIIC2 MIIC3 MIID0 MIID1 LED SUM MII Register Option 0 MII Register Option 1 Feature Registers MII Command Register 0 MII Command Register 1 MII Command Register 2 MII Command Register 3 MII Data Register 0 MII Data Register 1 LED Control Register EEPROM Checksum Register 600 601 602 603 604 605 606 607 608 609 60B R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W 0F0 0F1 0F2 N/A N/A N/A N/A N/A N/A 0F3 0FF 000 000 010 000 000 000 000 N/A N/A 000 000
6. Port Mirroring Controls MIRROR1_SRC MIRROR1_ DEST MIRROR2_SRC MIRROR2_ DEST Port Mirror 1 Source Port Port Mirror 1 Destination Port Port Mirror 2 Source Port Port Mirror 2 Destination Port 700 701 702 703 R/W R/W R/W R/W N/A N/A N/A N/A 07F 017 0FF 000
F. Device Configuration Register GCR DCR DCR1 DPST DTST DA Global Control Register Device Status and Signature Register Giga Port status Device Port Status Register Data read back register DA Register F00 F01 F02 F03 F04 FFF R/W RO RO R/W RO RO N/A N/A N/A N/A N/A N/A 000 N/A N/A 000 N/A DA
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13.2 13.2.1
* * I 2C
Data Sheet
Group 0 Address MAC Ports Group ECR1Pn: Port N Control Register
Address h000-01A; CPU Address: 0000+2xN Accessed by serial interface and I2C (R/W) 7 6 5 A-FC * * 4 3 2 Port Mode 1 0
Sp State Bit [0]
1 - Flow Control Off 0 - Flow Control On
* When Flow Control On: * In half duplex mode, the MAC transmitter applies back pressure for flow control. * In full duplex mode, the MAC transmitter sends Flow Control frames when necessary. The MAC receiver interprets and processes incoming flow control frames. The Flow Control Frame Received counter is incremented whenever a flow control is received. * When Flow Control off: * In half duplex mode, the MAC Transmitter does not assert flow control by sending flow control frames or jamming collision. * In full duplex mode, the Mac transmitter does not send flow control frames. The MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Received counter is not incremented.
Bit [1] Bit [2] Bit [4:3]
* * * * * * * *
1 - Half Duplex - Only 10/100 mode 0 - Full Duplex 1 - 10Mbps 0 - 100Mbps 00 - Automatic Enable Auto Neg. This enables hardware state machine for auto-negotiation. 01 - Limited Disable auto Neg. This disables hardware for speed autonegotiation. Poll MII for link status. 10 - Link Down. Disable auto Neg. state machine and force link down (disable the port) 11 - Link Up. User ERC1 [2:0] for config. Asymmetric Flow Control Enable
* 0 - Disable asymmetric flow control * 1 - Enable asymmetric flow control
Bit [5]
*
*
Asymmetric Flow Control Enable. When this bit is set and flow control is on (bit[0] = 0, don't send out a flow control frame. But MAC receiver interprets and process flow control frames. Default is 0 SS - Spanning tree state Default is 11
* * * * 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned.
Bit [7:6]
*
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Data Sheet
13.2.2
* *
MVTX2603
ECR2Pn: Port N Control Register
I2C Address: h01B-035; CPU Address: h0001+2xN Accessed by and serial interface and I2C (R/W) 7 6 5 4 3 Reserve 2 DisL 1 Ftf 0 Futf
QoS Sel Bit[0]: *
Filter untagged frame (Default 0)
* 0: Disable * 1: All untagged frames from this port are discarded
Bit[1]:
*
Filter Tag frame (Default 0)
* 0: Disable * 1: All tagged frames from this port are discarded
Bit[2]:
*
Learning Disable (Default 0)
* 1 Learning is disabled on this port * 0 Learning is enabled on this port
Bit[3]: Bit [5:4:]
* * * *
Must be set to `1' QOS mode selection (Default 00) Determines which of the 4 sets of QoS settings is used for 10/100 ports. Note that there are 4 sets of per-queue byte thresholds, and 4 sets of WFQ ratios programmed. These bits select among the 4 choices for each 10/100 port. Refer to QoS Application Note.
* * * * 00: select class byte limit set 0 and classes WFQ credit set 0 01: select class byte limit set 1 and classes WFQ credit set 1 10: select class byte limit set 2 and classes WFQ credit set 2 11: select class byte limit set 3 and classes WFQ credit set 3
Bit[7:6]
*
Reserved
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13.2.3
* *
Data Sheet
GGControl - Extra GIGA Port Control
CPU Address: h036 Accessed by serial interface (R/W) 7 DF 6 5 MiiB 4 RstA 3 DF 2 1 MiiA 0 RstA
Bit[0]:
*
Reset GIGA port A
* 0: Normal operation (default) * 1: Reset Gigabit port A
Bit[1]:
*
GIGA port A use MII interface (10/100M)
* 0: Gigabit port operations at 1000 mode * 1: Gigabit port operations at 10/100 mode
Bit[2]: Bit[3]:
* *
Reserved - Must be zero GIGA port A direct flow control (MAC to MAC connection). The MVTX2603 supports direct flow control mechanism, the flow control frame is therefore not sent through the Gigabit port data path.
* 0: Direct flow control disabled (default) * 1: Direct flow control enabled
Bit[4]:
*
Reset GIGA port B
* 0: Normal operation (default) * 1: Reset Gigabit port B
Bit[5]:
*
GIGA port B use MII interface (10/100M)
* 0: Gigabit port operates at 1000 mode * 1: Gigabit port operates at 10/100 mode
Bit[6]: Bit[7]:
* *
Reserved. Must be zero. GIGA port B direct flow control (MAC to MAC connection). The MVTX2603 supports direct flow control mechanism, the flow control frame is therefore not sent through the Gigabit port data path.
* 0: Direct flow control disabled (default) * 1: Direct flow control enabled
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Data Sheet
13.3 13.3.1
* * I 2C
MVTX2603
Group 1 Address VLAN Group AVTCL - VLAN Type Code Register Low
Address h036; CPU Address: h100 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00)
13.3.2
* *
AVTCH - VLAN Type Code Register High
I2C Address h037; CPU Address: h101 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81)
13.3.3
* *
PVMAP00_0 - Port 00 Configuration Register 0
I2C Address h038, CPU Address: h102 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLAN Mask for ports 7 to 0 (Default FF)
This register indicates the legal egress ports. A "1" on bit 7 means that the packet can be sent to port 7. A "0" on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1, 2 and 3 to form a 27 bit mask to all egress ports.
13.3.4
* *
PVMAP00_1 - Port 00 Configuration Register 1
I2C Address h39, CPU Address: h103 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLAN Mask for ports 15 to 8 (Default is FF)
13.3.5
* * I 2C
PVMAP00_2 - Port 00 Configuration Register 2
Address h3A, CPU Address: h104 Accessed by serial interface and I2C (R/W) Bit [7:0]: * VLAN Mask for ports 23 to 16 (Default FF)
13.3.6
* * I 2C
PVMAP00_3 - Port 00 Configuration Register 3
Address h3b, CPU Address: h105 Accessed by serial interface and I2C (R/W) 7 FP en 6 Drop 5 3 Default tx priority 2 1 VLAN Mask 0
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Bit [0]: Bit [2:1]: Bit [5:1]: Reserved (Default 1) VLAN Mask for ports 26 to 25 (Default 3) Default Transmit priority. Used when Bit[7] = 1 (Default 0) * 000 Transmit Priority Level 0 (Lowest) * 001 Transmit Priority Level 1 * 010 Transmit Priority Level 2 * 011 Transmit Priority Level 3 * 100 Transmit Priority Level 4 * 101 Transmit Priority Level 5 * 110 Transmit Priority Level 6 * 111 Transmit Priority Level 7 (Highest) Default Discard priority (Default 0) * 0 - Discard Priority Level 0 (Lowest) * 1 - Discard Priority Level 7(Highest)
Data Sheet
Bit [6]:
Bit [7]:
Enable Fix Priority (Default 0) * 0 Disable fix priority. All frames are analysed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS field or Logical Port. * 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3]
13.4
* * * * * * * * * * * * * * * * * * * * * * *
Port Configuration Register
PVMAP01_0,1,2,3 I2C Address h3C,3D,3E,3F; CPU Address:h106,107,108,109) PVMAP02_0,1,2,3 I2C Address h40,41,42,43; CPU Address:h10A, 10B, 10C, 10D) PVMAP03_0,1,2,3 I2C Address h44,45,46,47; CPU Address:h10E, 10F, 110, 111) PVMAP04_0,1,2,3 I2C Address h48,49,4A,4B; CPU Address:h112, 113, 114, 115) PVMAP05_0,1,2,3 I2C Address h4C,4D,4E,4F; CPU Address:h116, 117, 118, 119) PVMAP06_0,1,2,3 I2C Address h50,51,52,53; CPU Address:h11A, 11B, 11C, 11D) PVMAP07_0,1,2,3 I2C Address h54,55,56,57; CPU Address:h11E, 11F, 120, 121) PVMAP08_0,1,2,3 I2C Address h58,59,5A,5B; CPU Address:h122, 123, 124, 125) PVMAP09_0,1,2,3 I2C Address h5C,5D,5E,5F; CPU Address:h126, 127, 128, 129) PVMAP10_0,1,2,3 I2C Address h60,61,62,63; CPU Address:h12A, 12B, 12C, 12D) PVMAP11_0,1,2,3 I2C Address h64,65,66,67; CPU Address:h12E, 12F, 130, 131) PVMAP12_0,1,2,3 I2C Address h68,69,6A,6B; CPU Address:h132, 133, 134, 135) PVMAP13_0,1,2,3 I2C Address h6C,6D,6E,6F; CPU Address:h136, 137, 138, 139) PVMAP14_0,1,2,3 I2C Address h70,71,72,73; CPU Address:h13A, h13B, 13C, 13D) PVMAP15_0,1,2,3 I2C Address h74,75,76,77; CPU Address:h13E, 13F, 140, 141) PVMAP16_0,1,2,3 I2C Address h78,79,7A,7B; CPU Address:h142, 143, 144, 145) PVMAP17_0,1,2,3 I2C Address h7C,7D,7E,7F; CPU Address:h146, 147, 148, 149) PVMAP18_0,1,2,3 I2C Address h80,81,82,83; CPU Address:h14A, 14B, 14C, 14D) PVMAP19_0,1,2,3 I2C Address h84,85,86,87; CPU Address:h14E, 14F, 150, 151) PVMAP20_0,1,2,3 I2C Address h88,89,8A,8B; CPU Address:h152, 153, 154, 155) PVMAP21_0,1,2,3 I2C Address h8C,8D,8E,8F; CPU Address:h156, 157, 158, 159) PVMAP22_0,1,2,3 I2C Address h90,91,92,93; CPU Address:h15A, 15B, 15C, 15D) PVMAP23_0,1,2,3 I2C Address h94,95,96,97; CPU Address:h15E, 15F, 160, 161)
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Data Sheet
* *
MVTX2603
PVMAP25_0,1,2,3 I2C Address h9C,9D,9E,9F; CPU Address:h166, 167, 168, 169) (Gigabit port 1) PVMAP26_0,1,2,3 I2C Address hA0,A1,A2,A3; CPU Address:h16A, 16B, 16C, 16D) (Gigabit port 2)
13.4.1
* * I 2C
PVMODE
Address: h0A4, CPU Address: h170 Accessed by serial interface, and I2C (R/W) 7 5 4 SM0 Bit [0]: Bit [1]: * * * Reserved Must be `0' Slow learning Same function as SE_OP MODE bit 7. Either bit can enable the function; both need to be turned off to disable the feature. Disable dropping frames with destination MAC addresses 0180C2000001 to 0180C200000F
* 0: Drop all frames in the range * 1: Treats frames as multicast
3 rPCS
2 DF
1 SL
0
Bit [2]:
*
Bit [3]: Bit [4]: *
* 1: Disable reset PCS * 0: Enable reset PCS. PCS FIFO will be reset when receiving a PCS symbol error.
Support MAC address 0
* 0: MAC address 0 is not learned. * 1: MAC address 0 is learned.
Bit [7:5]:
*
Reserved
13.4.2
* *
TRUNK0_MODE- Trunk group 0 mode
I2C Address: h0A5; CPU Address: h203 Accessed by serial interface and I2C (R/W) 7 4 3 2 1 0
Hash Select Bit [1:0]: *
Port Select
Port selection in unmanaged mode. Input pin TRUNK0 enable/disable trunk group 0.
* * * * 00 Reserved 01 Port 0 and 1 are used for trunk 0 10 Port 0,1 and 2 are used for trunk 0 11 Port 0,1,2 and 3 are used for trunk 0
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Bit [3:2] *
Data Sheet
Hash Select. The Hash selected is valid for Trunk 0, 1 and 2. (Default 00)
* * * * 00 Use Source and Destination Mac Address for hashing 01 Use Source Mac Address for hashing 10 Use Destination Mac Address for hashing 11 Use source destination MAC address and ingress physical port number for hashing
Note: Trunk group 2 (two gigabit ports) is enabled/disabled using input pin TRUNK2.
13.4.3
* * I 2C
TRUNK1_MODE - Trunk group 1 mode
Address: h0A6; CPU Address: h20B Accessed by serial interface and I2C (R/W) 7 2 1 0 Port Select Bit [1:0]: * * * * * Port selection in unmanaged mode. Input pin TRUNK1 enable/disable trunk group 1. 00 Reserved 01 Port 4 and 5 are used for trunk1 10 Reserved 11 Port 4,5,6 and 7 are used for trunk1
13.5 13.5.1
* * I 2C
Group 4 Address Search Engine Group TX_AGE - Tx Queue Aging timer
Address: h07;CPU Address: h325 Accessed by serial interface (RW) 7 6 5 Tx Queue Agent 0
* * *
Bit[5:0]: Unit of 100ms (Default 8) Disable transmission queue aging if value is zero. Aging timer for all ports and queues. For no packet loss flow control, this register must be set to 0.
13.5.2
* * * *
AGETIME_LOW - MAC address aging time Low
I2C Address: h0A8; CPU Address: h400 Accessed by serial interface and I2C (R/W) Bit [7:0] Low byte of the MAC address aging timer. MAC address aging is enable/disable by boot strap TSTOUT9
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Data Sheet
13.5.3
* * * * *
MVTX2603
AGETIME_HIGH -MAC address aging time High
I2C Address: h0A9; CPU Address: h401 Accessed by serial interface and I2C (R/W) Bit [7:0]: High byte of the MAC address aging timer. The default setting provide 300 seconds aging time. Aging time is based on the following equation: {AGETIME_HIGH,AGETIME_LOW} X (# of MAC address entries in the memory x 100sec). Number of MAC entries = 32K when 1MB is used per bank. Number of MAC entries = 64K when 2MB is used per bank.
13.5.4
* * *
SE_OPMODE - Search Engine Operation Mode
CPU Address: h403 Accessed by serial interface (R/W) {SE_OPMODE} X(# of entries 100usec) 7 SL Bit [5:0]: Bit [6]: 6 DMS * * Reserved Disable MCT speedup aging
* 1 - Disable speedup aging when MCT resource is low. * 0 - Enable speedup aging when MCT resource is low.
5
0
Bit [7]:
*
Slow Learning
* 1- Enable slow learning. Learning is temporary disabled when search demand is high * 0 - Learning is performed independent of search demand
13.6 13.6.1
*
Group 5 Address Buffer Control/QOS Group FCBAT - FCB Aging Timer
I2C Address: h0AA; CPU Address: h500 7 FCBAT Bit [7:0]: * * FCB Aging time. Unit of 1ms. (Default FF) This function is for buffer aging control. It is used to configure the aging time, and can be enabled/ disabled through bootstrap pin. It is not recommended to use this function for normal operation. 0
13.6.2
* * I 2C
QOSC - QOS Control
Address: h0AB; CPU Address: h501 Accessed by serial interface and I2C (R/W) 7 Tos-d 6 Tos-p 5 4 VF1c 3 1 0 L
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MVTX2603
Bit [0]: Bit [4]: * *
Data Sheet
QoS frame lost is OK. Priority will be available for flow control enabled source only when this bit is set (Default 0) Per VLAN Multicast Flow Control (Default 0)
* 0 - Disable * 1 - Enable
Bit [5]: Bit [6]:
* *
Reserved Select TOS bits for Priority (Default 0)
* 0 - Use TOS [4:2] bits to map the transmit priority * 1 - Use TOS [7:5] bits to map the transmit priority
Bit [7]:
*
Select TOS bits for Drop Priority (Default 0)
* 0 - Use TOS[4:2] bits to map the drop priority * 1 - Use TOS[7:5] bits to map the drop priority
13.6.3
* * I 2C
FCR - Flooding Control Register
Address: h0AC; CPU Address: h502 Accessed by serial interface and I2C (R/W) 7 Tos Bit [3:0]: * 6 TimeBase 4 3 U2MR 0
U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used to limit the amount of flooding traffic. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 8) TimeBase: 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 100us (same as 000)
Bit [6:4]:
*
* Bit [7]: *
(Default = 000) Select VLAN tag or TOS (IP packets) to be preferentially picked to map transmit priority and drop priority (Default = 0).
* 0 - Select VLAN Tag priority field over TOS * 1 - Select TOS over VLAN tag priority field
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Data Sheet
13.6.4
* *
MVTX2603
AVPML - VLAN Priority Map
I2C Address: h0AD; CPU Address: h503 Accessed by serial interface and I2C (R/W) 7 VP2 6 5 VP1 3 2 VP0 0
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit priorities. Under the internal transmit priority, seven is highest priority where as zero is the lowest. This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map VLAN priority 0 into internal transmit priority 7. The new priority is used inside the 2603. When the packet goes out it carries the original priority. Bit [2:0]: Bit [5:3]: Bit [7:6]: * * * Priority when the VLAN tag priority field is 0 (Default 0) Priority when the VLAN tag priority field is 1 (Default 0) Priority when the VLAN tag priority field is 2 (Default 0)
13.6.5
* * I 2C
AVPMM - VLAN Priority Map
Address: h0AE, CPU Address: h504 Accessed by serial interface and I2C (R/W) 7 VP5 6 VP4 4 3 VP3 1 0 VP2
*
Map VLAN priority into eight level transmit priorities: Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Priority when the VLAN tag priority field is 2 (Default 0) Priority when the VLAN tag priority field is 3 (Default 0) Priority when the VLAN tag priority field is 4 (Default 0) Priority when the VLAN tag priority field is 5 (Default 0)
13.6.6
* * I 2C
AVPMH - VLAN Priority Map
Address: h0AF, CPU Address: h505 Accessed by serial interface and I2C (R/W) 7 VP7 5 4 VP6 2 1 VP5 0
Map VLAN priority into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Priority when the VLAN tag priority field is 5 (Default 0) Priority when the VLAN tag priority field is 6 (Default 0) Priority when the VLAN tag priority field is 7 (Default 0)
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13.6.7
* *
Data Sheet
TOSPML - TOS Priority Map
I2C Address: h0B0, CPU Address: h506 Accessed by serial interface and I2C (R/W) 7 TP2 6 5 TP1 3 2 TP0 0
Map TOS field in IP packet into eight level transmit priorities Bit [2:0]: Bit [5:3]: Bit [7:6]: * * Priority when the TOS field is 0 (Default 0) Priority when the TOS field is 1 (Default 0)
Priority when the TOS field is 2 (Default 0)
13.6.8
* *
TOSPMM - TOS Priority Map
I2C Address: h0B1, CPU Address: h507 Accessed by serial interface and I2C (R/W) 7 TP5 6 TP4 4 3 TP3 1 0 TP2
Map TOS field in IP packet into four level transmit priorities Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Priority when the TOS field is 2 (Default 0) Priority when the TOS field is 3 (Default 0) Priority when the TOS field is 4 (Default 0) Priority when the TOS field is 5 (Default 0)
13.6.9
* * I 2C
TOSPMH - TOS Priority Map
Address: h0B2, CPU Address: h508 Accessed by serial interface and I2C (R/W) 7 TP7 5 4 TP6 2 1 TP5 0
Map TOS field in IP packet into four level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Priority when the TOS field is 5 (Default 0) Priority when the TOS field is 6 (Default 0) Priority when the TOS field is 7 (Default 0)
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Data Sheet
13.6.10 AVDM - VLAN Discard Map
* * I2C Address: h0B3, CPU Address: h509 Accessed by serial interface and I2C (R/W) 7 FDV7 6 FDV6 5 FDV5 4 FDV4 3 FDV3 2 FDV2 1 FDV1 0 FDV0
MVTX2603
Map VLAN priority into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: * * * * * * * * Frame drop priority when VLAN tag priority field is 0 (Default 0) Frame drop priority when VLAN tag priority field is 1 (Default 0) Frame drop priority when VLAN tag priority field is 2 (Default 0) Frame drop priority when VLAN tag priority field is 3 (Default 0) Frame drop priority when VLAN tag priority field is 4 (Default 0) Frame drop priority when VLAN tag priority field is 5 (Default 0) Frame drop priority when VLAN tag priority field is 6 (Default 0) Frame drop priority when VLAN tag priority field is 7 (Default 0)
13.6.11 TOSDML - TOS Discard Map
* * I2C Address: h0B4, CPU Address: h50A Accessed by serial interface and I2C (R/W) 7 FDT7 6 FDT6 5 FDT5 4 FDT4 3 FDT3 2 FDT2 1 FDT1 0 FDT0
Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: * * * * * * * * Frame drop priority when TOS field is 0 (Default 0) Frame drop priority when TOS field is 1 (Default 0) Frame drop priority when TOS field is 2 (Default 0) Frame drop priority when TOS field is 3 (Default 0) Frame drop priority when TOS field is 4 (Default 0) Frame drop priority when TOS field is 5 (Default 0) Frame drop priority when TOS field is 6 (Default 0) Frame drop priority when TOS field is 7 (Default 0)
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13.6.12 BMRC - Broadcast/Multicast Rate Control
* * I2C Address: h0B5, CPU Address: h50B Accessed by serial interface and I2C (R/W) 7 Broadcast Rate * 4 3 Multicast Rate 0
Data Sheet
This broadcast and multicast rate defines for each port the number of packet allowed to be forwarded within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Timebase is based on register 502 [6:4]. Bit [3:0]: * Multicast Rate Control Number of multicast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0). Broadcast Rate Control Number of broadcast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0)
Bit [7:4]:
*
13.6.13 UCC - Unicast Congestion Control
* * I2C Address: h0B6, CPU Address: h50C Accessed by serial interface and I2C (R/W) 7 Unicast congest threshold Bit [7:0]: * Number of frame count. Used for best effort dropping at B% when destination port's best effort queue reaches UCC threshold and shared pool is all in use. Granularity 1 frame. (Default: h10 for 2 MB/bank or h08 for 1 MB/bank) 0
13.6.14 MCC - Multicast Congestion Control
* * I2C Address: h0B7, CPU Address: h50D Accessed by serial interface and I2C (R/W) 7 FC reaction prd Bit [4:0]: * 5 4 Multicast congest threshold 0
In multiples of two. Used for triggering MC flow control when destination multicast port's best effort queue reaches MCC threshold. (Default 0x10) Flow control reaction period (Default 2) Granularity 4uSec.
Bit [7:5]:
*
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Data Sheet
13.6.15 PR100 - Port Reservation for 10/100 ports
* * I2C Address: h0B8, CPU Address: h50E Accessed by serial interface and I2C (R/W) 7 Buffer low thd Bit [3:0]: * * 4 3 SP Buffer reservation 0
MVTX2603
Per port buffer reservation. Define the space in the FDB reserved for each 10/100 port. Expressed in multiples of 4 packets. For each packet 1536 bytes are reserved in the memory. Expressed in multiples of 4 packets. Threshold for dropping all best effort frames when destination port best efforts queues reach UCC threshold and shared pool all used and source port reservation is at or below the PR100[7:4] level. Also the threshold for initiating UC flow control. Default:
* h36 for 24+2 configuration with memory 2MB/bank; * h24 for 24+2 configuration with 1MB/bank;
Bits [7:4]:
*
*
13.6.16 PRG - Port Reservation for Giga ports
* * I2C Address: h0B9, CPU Address: h50F Accessed by serial interface and I2C (R/W) 7 Buffer low thd Bit [3:0]: * * 3 SP buffer reservation 0
Per source port buffer reservation. Define the space in the FDB reserved for each Gigabit port. Expressed in multiples of 16 packets. For each packet 1536 bytes are reserved in the memory. Expressed in multiples of 16 packets. Threshold for dropping all best effort frames when destination port best effort queues reach UCC threshold and shared pool is all used and source port reservation is at or below the PRG[7:4] level. Also the threshold for initiating UC flow control. Default:
* H58 for memory 2MB/bank; * H35 for 1MB/bank;
Bits [7:4]:
*
*
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13.6.17 SFCB - Share FCB Size
* * I2C Address: h0BA, CPU Address: h510 Accessed by serial interface and I2C (R/W) 7 Shared buffer size Bits [7:0]: * * 0
Data Sheet
Expressed in multiples of 4 packets. Buffer reservation for shared pool. Default:
* h64 for 24+2 configuration with memory of 2MB/bank; * h14 for 24+2 configuration with memory of 1MB/bank;
13.6.18 C2RS - Class 2 Reserve Size
* * I2C Address: h0BB, CPU Address: h511 Accessed by serial interface and I2C (R/W) 7 Class 2 FCB Reservation * Buffer reservation for class 2 (third lowest priority). Granularity 1. (Default 0) 0
13.6.19 C3RS - Class 3 Reserve Size
* * I2C Address: h0BC, CPU Address: h512 Accessed by serial interface and I2C (R/W) 7 Class 3 FCB Reservation * Buffer reservation for class 3. Granularity 1. (Default 0) 0
13.6.20 C4RS - Class 4 Reserve Size
* * I2C Address: h0BD, CPU Address: h513 Accessed by serial interface and I2C (R/W) 7 Class 4 FCB Reservation * Buffer reservation for class 4. Granularity 1. (Default 0) 0
13.6.21 C5RS - Class 5 Reserve Size
* * I2C Address: h0BE; CPU Address: h514 Accessed by serial interface and I2C (R/W) 7 Class 5 FCB Reservation * Buffer reservation for class 5. Granularity 1. (Default 0) 0
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Data Sheet
13.6.22 C6RS - Class 6 Reserve Size
* * I2C Address: h0BF; CPU Address h515 Accessed by serial interface and I2C (R/W) 7 Class 6 FCB Reservation * Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0) I2C Address: h0C0; CPU Address: h516 Accessed by serial interface and I2C (R/W) 7 Class 7 FCB Reservation * Buffer reservation for class 7 (highest priority). Granularity 1. (Default 0) Accessed by serial interface and I2C (R/W) C -- QOSC00 - BYTE_C01 (I2C Address h0C1, CPU Address 517) B -- QOSC01 - BYTE_C02 (I2C Address h0C2, CPU Address 518) A -- QOSC02 - BYTE_C03 (I2C Address h0C3, CPU Address 519) 0 0
MVTX2603
13.6.23 C7RS - Class 7 Reserve Size
* *
13.6.24 Classes Byte Limit Set 0
* * * *
QOSC00 through QOSC02 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Drop (WRED) Scheme described in Chapter 7.7. There are four such sets of values A-C specified in Classes Byte Limit Set 0, 1, 2, and 3. Each 10/ 100 port can choose one of the four Byte Limit Sets as specified by the QoS Select field located in bits 5 to 4 of the ECR2n register. The values A-C are per-queue byte thresholds for random early drop. QOSC02 represents A, and QOSC00 represents C. Granularity when Delay bound is used: QOSC02: 128 bytes, QOSC01: 256 bytes. QOSC00: 512 bytes. Granularity when WFQ is used: QOSC02: 512 bytes, QOSC01: 512 bytes, QOSC00: 512 bytes.
13.6.25 Classes Byte Limit Set 1
* Accessed by serial interface and I2C (R/W) C - QOSC03 - BYTE_C11 (I2C Address h0C4, CPU Address 51a) B - QOSC04 - BYTE_C12 (I2C Address h0C5, CPU Address 51b) A - QOSC05 - BYTE_C13 (I2C Address h0C6, CPU Address 51c) QOSC03 through QOSC05 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC05: 128 bytes, QOSC04: 256 bytes. QOSC03: 512 bytes. Granularity when WFQ is used: QOSC05: 512 bytes, QOSC04: 512 bytes, QOSC03: 512 bytes.
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13.6.26 Classes Byte Limit Set 2
* Accessed by serial interface and I2C (R/W) C - QOSC06 - BYTE_C21 (CPU Address 51d) B - QOSC07 - BYTE_C22 (CPU Address 51e) A - QOSC08 - BYTE_C23 (CPU Address 51f)
Data Sheet
QOSC06 through QOSC08 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC08: 128 bytes, QOSC07: 256 bytes. QOSC06: 512 bytes. Granularity when WFQ is used: QOSC08: 512 bytes, QOSC07: 512 bytes, QOSC06: 512 bytes.
13.6.27 Classes Byte Limit Set 3
* Accessed by serial interface and I2C (R/W) C - QOSC09 - BYTE_C31 (CPU Address 520) B - QOSC10 - BYTE_C32 (CPU Address 521) A - QOSC11 - BYTE_C33 (CPU Address 522) QOSC09 through QOSC011 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC11: 128 bytes, QOSC10: 256 bytes. QOSC09: 512 bytes. Granularity when WFQ is used: QOSC11: 512 bytes, QOSC10: 512 bytes, QOSC09: 512 bytes.
13.6.28 Classes Byte Limit Giga Port 1
* Accessed by serial interface and I2C (R/W) F - QOSC12 - BYTE_C2_G1 (I2C Address h0C7, CPU Address 523) E - QOSC13 - BYTE_C3_G1 (I2C Address h0C8, CPU Address 524) D - QOSC14 - BYTE_C4_G1 (I2C Address h0C9, CPU Address 525) C - QOSC15 - BYTE_C5_G1 (I2C Address h0CA, CPU Address 526) B - QOSC16 - BYTE_C6_G1 (I2C Address h0CB, CPU Address 527) A - QOSC17 - BYTE_C7_G1 (I2C Address h0CC, CPU Address 528) QOSC12 through QOSC17 represent the values A-F for Gigabit port 24. They are per-queue byte thresholds for random early drop. QOSC17 represents A, and QOSC12 represents F. Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes, QOSC13 and QOSC12: 1024 bytes. Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes
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Data Sheet
13.6.29 Classes Byte Limit Giga Port 2
* Accessed by serial interface and I2C (R/W) F - QOSC18 - BYTE_C2_G2 (I2C Address h0CD, CPU Address 529) E - QOSC19 - BYTE_C3_G2 (I2C Address h0CE, CPU Address 52a) D - QOSC20 - BYTE_C4_G2 (I2C Address h0CF, CPU Address 52b) C - QOSC21 - BYTE_C5_G2 (I2C Address h0D0, CPU Address 52c) B - QOSC22 - BYTE_C6_G2 (I2C Address h0D1, CPU Address 52d) A - QOSC23 - BYTE_C7_G2 (I2C Address h0D2, CPU Address 52e)
MVTX2603
QOSC18 through QOSC23 represent the values A-F for Gigabit port 2. They are per-queue byte thresholds for random early drop. QOSC23 represents A, and QOSC18 represents F. Granularity when Delay Bound is used: QOSC23 and QOSC22: 256 bytes, QOSC21 and QOSC20: 512 bytes, QOSC19 and QOSC18: 1024 bytes. Granularity when WFQ is used: QOSC18 to QOSC23: 1024 bytes
13.6.30 Classes WFQ Credit Set 0
* Accessed by serial interface (R/W) W3 - QOSC24[5:0] - CREDIT_C00 (CPU Address 52f) W2 - QOSC25[5:0] - CREDIT_C01 (CPU Address 530) W1 - QOSC26[5:0] - CREDIT_C02 (CPU Address 531) W0 - QOSC27[5:0] - CREDIT_C03 (CPU Address 532) QOSC24 through QOSC27 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC27 corresponds to W0, and QOSC24 corresponds to W3. * QOSC24[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4. * QOSC25[7]: Priority service allow flow control for the ports select this parameter set. * QOSC25[6]: Flow control pause best effort traffic only Both flow control allow and flow control best effort only can take effect only the priority type is WFQ.
13.6.31 Classes WFQ Credit Set 1
* Accessed by serial interface (R/W) W3 - QOSC28[5:0] - CREDIT_C10 (CPU Address 533) W2 - QOSC29[5:0] - CREDIT_C11 (CPU Address 534) W1 - QOSC30[5:0] - CREDIT_C12 (CPU Address 535) W0 - QOSC31[5:0] - CREDIT_C13 (CPU Address 536) QOSC28 through QOSC31 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC31 corresponds to W0, and QOSC28 corresponds to W3. QOSC28[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4. QOSC29[7]: Priority service allow flow control for the ports select this parameter set. QOSC29[6]: Flow control pause best effort traffic only
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13.6.32 Classes WFQ Credit Set 2
* Accessed by serial interface (R/W) W3 - QOSC32[5:0] - CREDIT_C20 (CPU Address 537) W2 - QOSC33[5:0] - CREDIT_C21 (CPU Address 538) W1 - QOSC34[5:0] - CREDIT_C22 (CPU Address 539) W0 - QOSC35[5:0] - CREDIT_C23 (CPU Address 53a)
Data Sheet
QOSC35 through QOSC32 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC35 corresponds to W0, and QOSC32 corresponds to W3. * * * QOSC32[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC33[7]: Priority service allow flow control for the ports select this parameter set. QOSC33[6]: Flow Control pause best effort traffic only
13.6.33 Classes WFQ Credit Set 3
* Accessed by serial interface (R/W) W3 - QOSC36[5;0] - CREDIT_C30 (CPU Address 53b) W2 - QOSC37[5:0] - CREDIT_C31 (CPU Address 53c) W1 - QOSC38[5:0] - CREDIT_C32 (CPU Address 53d) W0 - QOSC39[5:0] - CREDIT_C33 (CPU Address 53e) QOSC39 through QOSC36 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC39 corresponds to W0, and QOSC36 corresponds to W3. * * * QOSC36[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC37[7]: Priority service allow flow control for the ports select this parameter set. QOSC37[6]: Flow Control pause best effort traffic only
13.6.34 Classes WFQ Credit Port G1
* Accessed by serial interface (R/W) W7 - QOSC40[5:0] - CREDIT_C0_G1 (CPU Address 53F) [7:6] - Priority service type. Option 1 to 4. W6 - QOSC41[5:0] - CREDIT_C1_G1 (CPU Address 540) [7]: Priority service allow flow control for the ports select this parameter set. [6]: Flow Control pause best effort traffic only W5 - QOSC42[5:0] - CREDIT_C2_G1 (CPU Address 541) W4 - QOSC43[5:0] - CREDIT_C3_G1 (CPU Address 542) W3 - QOSC44[5:0] - CREDIT_C4_G1 (CPU Address 543) W2 - QOSC45[5:0] - CREDIT_C5_G1 (CPU Address 544) W1 - QOSC46[5:0] - CREDIT_C6_G1 (CPU Address 545) W0 - QOSC47[5:0] - CREDIT_C7_G1 (CPU Address 546) QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. The granularity of the numbers is 1, and their sum must be 64. QOSC47 corresponds to W0, and QOSC40 corresponds to W7. In the 2G trunk configuration, the sum of all values QOSC40 through QOSC47 must equal 128.
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Data Sheet
13.6.35 Classes WFQ Credit Port G2
* Accessed by serial interface (R/W) W7 - QOSC48[5:0] - CREDIT_C0_G2 (CPU Address 547) [7:6] - Priority service type. Option 1 to 4. W6 - QOSC49[5:0] - CREDIT_C1_G2 (CPU Address 548) [7]: Priority service allow flow control for the ports select this parameter set. [6]: Flow Control pause best effort traffic only W5 - QOSC50[5:0] - CREDIT_C2_G2 (CPU Address 549) W4 - QOSC51[5:0] - CREDIT_C3_G2 (CPU Address 54a) W3 - QOSC52[5:0] - CREDIT_C4_G2 (CPU Address 54b) W2 - QOSC53[5:0] - CREDIT_C5_G2 (CPU Address 54c) W1 - QOSC54[5:0] - CREDIT_C6_G2 (CPU Address 54d) W0 - QOSC55[5:0] - CREDIT_C7_G2 (CPU Address 54e)
MVTX2603
QOSC48 through QOSC55 represents the set of WFQ parameters for Gigabit port 25. The granularity of the numbers is 1, and their sum must be 64. QOSC55 corresponds to W0, and QOSC48 corresponds to W7. In the 2G trunk configuration, the sum of all values QOSC48 through QOSC55 must equal 128.
13.6.36 Class 6 Shaper Control Port G1
* Accessed by serial interface (R/W)
* QOSC56[5:0] - TOKEN_RATE_G1 (Address 54f). Programs the average rate for Gigabit port 1. When equal to 0, shaper is disable. Granularity is 1. * QOSC57[7:0] - TOKEN_LIMIT_G1 (Address 550). Programs the maximum counter for Gigabit port1. Granularity is 16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is limited to gigabit ports and queue P6 when it is in strict priority. QOSC41 programs the peak rate for Gigabit port 1. See Programming QoS Registers application note for more information.
13.6.37 Class 6 Shaper Control Port G2
* Accessed by serial interface (R/W)
* QOSC58[5:0] - TOKEN_RATE_G2 (CPU Address 551). Programs the average rate for Gigabit port 2. When equal to 0, shaper is disable. Granularity is 1. * QOSC59[7:0] - TOKEN_LIMIT_G2 (CPU Address 552). Programs the maximum counter for Gigabit port2. Granularity is 16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is limited to gigabit ports and queue P6 when it is in strict priority. QOSC49 programs the peak rate for Gigabit port 2. See Programming QoS Registers application note for more information.
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13.6.38 RDRC0 - WRED Rate Control 0
* * I2C Address: h0FB, CPU Address: h553 Accessed by serial Interface and IcC (R/W) 7 X Rate Bits [7:4]: Bits[3:0]: * * 4 3 Y Rate 0
Data Sheet
Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%. Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%.
See Programming QoS Registers application note for more information.
13.6.39 RDRC1 - WRED Rate Control 1
* * I2C Address: h0FC, CPU Address: h554 Accessed by serial Interface and I2C (R/W) 7 Z Rate Bits [7:4]: Bits[3:0]: * * 4 3 B Rate 0
Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%. Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and destination port best effort queue reaches UCC. Granularity 6.25%.
See Programming QoS Register application note for more information.
13.6.40 User Defined Logical Ports and Well Known Ports
The MVTX2603 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are * 0:23 * 1:512 * 2:6000 * 3:443 * 4:111 * 5:22555 * 6:22 * 7:554 Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_ Enable can individually turn on/off each Well Known Port if desired. Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7 registers. Two registers are required to be programmed for the logical port number. The respective priority
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Data Sheet
MVTX2603
can be programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in RPRIORITY.
13.6.40.1USER_PORT0_(0~7) - User Define Logical Port (0~7)
* * * * * * * * * USER_PORT_0 - I2C Address h0D6 + 0DE; CPU Address 580(Low) + 581(High) USER_PORT_1 - I2C Address h0D7 + 0DF; CPU Address 582 + 583 USER_PORT_2 - I2C Address h0D8 + 0E0; CPU Address 584 + 585 USER_PORT_3 - I2C Address h0D9 + 0E1; CPU Address 586 + 587 USER_PORT_4 - I2C Address h0DA + 0E2; CPU Address 588 + 589 USER_PORT_5 - I2C Address h0DB + 0E3; CPU Address 58a + 58b USER_PORT_6 - I2C Address h0DC + 0E4; CPU Address 58c + 58d USER_PORT_7 - I2C Address h0DD + 0E5; CPU Address 58e + 58f Accessed by serial interface and I2C (R/W) 7 TCP/UDP Logic Port Low 7 TCP/UDP Logic Port High * (Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the definition of eight separate ports. I2C Address: h0E6, CPU Address: h590 Accessed by serial interface and I2C (R/W) 7 Priority 1 * The chip allows the definition of the priority Bits[3:0]: Bits [7:4]: * * Priority setting, transmission + dropping, for logic port 0 Priority setting, transmission + dropping, for logic port 1 (Default 00) 5 4 Drop 3 Priority 0 1 0 Drop 0 0
13.6.40.2USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
* *
13.6.40.3USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
* * I2C Address: h0E7, CPU Address: h591 Accessed by serial interface and I2C (R/W) 7 Priority 3 5 4 Drop 3 Priority 2 1 0 Drop
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13.6.40.4USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
* * I2C Address: h0E8, CPU Address: h592 Accessed by serial interface and I2C (R/W) 7 Priority 5 * * * (Default 00) I2C Address: h0E9, CPU Address: h593 Accessed by serial interface and I2C (R/W) 7 Priority 7 * * * (Default 00) I2C Address: h0EA, CPU Address: h594 Accessed by serial interface and I2C (R/W) 7 P7 * * * (Default 00) I2C Address: h0EB, CPU Address: h595 Accessed by serial interface and I2C (R/W) 7 Priority 1 * * * * * 5 4 Drop 3 Priority 0 1 0 Drop 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0 5 4 Drop 3 Priority 6 1 0 Drop 5 4 Drop 3 Priority 4 1 0 Drop
Data Sheet
13.6.40.5USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority
13.6.40.6USER_PORT_ENABLE [7:0] - User Define Logic 7 to 0 Port Enables
13.6.40.7WELL_KNOWN_PORT [1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority
Priority 0 - Well known port 23 for telnet applications. Priority 1 - Well known port 512 for TCP/UDP (Default 00) I2C Address: h0EC, CPU Address: h596 Accessed by serial interface and I2C (R/W) 7 Priority 3 5 4 Drop 3 Priority 2 1 0 Drop
13.6.40.8WELL_KNOWN_PORT [3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority
* * *
Priority 2 - Well known port 6000 for XWIN. Priority 3 - Well known port 443 for http. sec (Default 00)
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MVTX2603
13.6.40.9WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority
* * I2C Address: h0ED, CPU Address: h597 Accessed by serial interface and I2C (R/W) 7 Priority 5 * * * * * 5 4 Drop 3 Priority 4 1 0 Drop
Priority 4 - Well known port 111 for sun rpe. Priority 5 - Well known port 22555 for IP Phone call setup. (Default 00) I2C Address: h0EE, CPU Address: h598 Accessed by serial interface and I2C (R/W) 7 Priority 7 5 4 Drop 3 Priority 6 1 0 Drop
13.6.40.10WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority
* * * * *
Priority 6 - Well known port 22 for ssh. Priority 7 - Well known port 554 for rtsp. (Default 00) I2C Address: h0EF, CPU Address: h599 Accessed by serial interface and I2C (R/W) 7 P7
* 1 - Enable * 0 - Disable
13.6.40.11WELL KNOWN_PORT_ENABLE [7:0] - Well Known Logic 7 to 0 Port Enables
6 P6
5 P5
4 P4
3 P3
2 P2
1 P1
0 P0
* * * * * * * * * *
(Default 00) I2C Address: h0F4, CPU Address: h59a Accessed by serial interface and I2C (R/W) (Default 00) I2C Address: h0F5, CPU Address: h59b Accessed by serial interface and I2C (R/W) (Default 00) I2C Address: h0D3, CPU Address: h59c Accessed by serial interface and I2C (R/W) (Default 00)
13.6.40.12RLOWL - User Define Range Low Bit 7:0
13.6.40.13RLOWH - User Define Range Low Bit 15:8
13.6.40.14RHIGHL - User Define Range High Bit 7:0
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13.6.40.15RHIGHH - User Define Range High Bit 15:8
* * * * * I2C Address: h0D4, CPU Address: h59d Accessed by serial interface and I2C (R/W) (Default 00) I2C Address: h0D5, CPU Address: h59e Accessed by serial interface and I2C (R/W) 7 4 3 Range Transmit Priority * 1 0 Drop
Data Sheet
13.6.40.16RPRIORITY - User Define Range Priority
RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit[3:1] Bits[0]: * * Transmit Priority Drop Priority
13.7 13.7.1
* *
Group 6 Address MISC Group MII_OP0 - MII Register Option 0
I2C Address: hF0, CPU Address:h600 Accessed by serial interface and I2C (R/W) 7 hfc Bits [7]: * 6 1prst 5 DisJ 4 Vendor Spc. Reg Addr 0
Half duplex flow control feature
* 0 = Half duplex flow control always enable * 1 = Half duplex flow control by negotiation
Bits[6]: Bits[5]:
* *
Link partner reset auto-negotiate disable Disable jabber detection. This is for HomePNA application or any serial operation slower than 10Mbps.
* 1 = disable * 0 = enable
Bit[4:0]:
*
Vendor specified link status register address (null value means don't use it) (Default 00); used when the Linkup bit position in the PHY is non-standard.
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Data Sheet
13.7.2
* *
MVTX2603
MII_OP1 - MII Register Option 1
I2C Address: hF1, CPU Address:h601 Accessed by serial interface and I2C (R/W) 7 Speed bit location Bits[3:0]: Bits [7:4]: * * * 4 3 Duplex bit location 0
Duplex bit location in vendor specified register Speed bit location in vendor specified register (Default 00)
13.7.3
* *
FEN - Feature Register
I2C Address: hF2, CPU Address: h602 Accessed by serial interface and I2C (R/W) 7 DML Bits [1:0]: Bit [2]: * * * * * 6 MII Reserved (Default 0) Support DS EF Code. (Default 0) When 101110 is detected in DS field (TOS [7:2]), the frame priority is set for 110 and drop is set for 0. Reserved (Default 010) Disable MII Management State Machine
* 0: Enable MII Management State Machine (Default 0) * 1: Disable MII Management State Machine
5
3
2 DS
1
0
Bit [5:3]: Bit [6]:
Bit [7]:
*
Disable using MCT link list structure
* 0: Enable using MCT Link List structure (Default 0) * 1: Disable using MCT Link List structure
13.7.4
MIIC0 - MII Command Register 0
* CPU Address: h603 * Accessed by serial interface only (R/W) * Bit [7:0] MII Data [7:0] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command.
13.7.5
MIIC1 - MII Command Register 1
* CPU Address: h604 * Accessed by serial interface only (R/W) * Bit [7:0] MII Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command.
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MVTX2603
13.7.6
* *
Data Sheet
MIIC2 - MII Command Register 2
CPU Address :h605 Accessed by serial interface only (R/W) 7 6 Mii OP Bits [4:0]: Bit [6:5] * * 5 4 Register address 0
REG_AD - Register PHY Address OP - Operation code "10" for read command and "01" for write command
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Writing to this register will initiate a serial management cycle to the MII management interface. For detail information, please refer to the PHY Control Application Note.
13.7.7
* *
MIIC3 - MII Command Register 3
CPU Address: h606 Accessed by serial interface only (R/W) 7 Rdy Bits [4:0]: Bit [6] Bit [7] * * * 6 Valid PHY_AD - 5 Bit PHY Address VALID - Data Valid from PHY (Read Only) RDY - Data is returned from PHY (Ready Only) 5 4 PHY address 0
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command.
13.7.8
* * *
MIID0 - MII Data Register 0
CPU Address: h607 Accessed by serial interface only (RO) Bit [7:0] MII Data [7:0]
13.7.9
* * *
MIID1 - MII Data Register 1
CPU Address: h608 Accessed by serial interface only (RO) Bit [7:0] MII Data [15:8]
13.7.10 LED Mode - LED Control
* * CPU Address: h609 Accessed by serial interface and I2C (R/W) 7 5 4 Clock rate 3 2 Hold Time 1 0
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Data Sheet
Bit [0] Bit[2:1]: * * Reserved (Default 0) Hold time for LED signal (Default= 00)
* 00=8msec 01=16msec 10=32msec 11=64msec
MVTX2603
Bit[4:3]:
* LED clock frequency (Default 0) For 100MHz SCLK 00=100M/8=12.5 MHz 10=100M/32=3.125 MHz For 125MHz SCLK 00=125M/64=1953 KHz 10=125M/512=244 KHz 01=125M/128=977KHz 11=125M/1024=122KHz 01=100M/16= 6.25 MHz 11=100M/64=1.5625 MHz
Bit[7:6]:
*
Reserved. Must be 0. (Default 0)
13.7.11 CHECKSUM - EEPROM Checksum
* * I2C Address: FF, CPU Address: h60b Accessed by serial interface and I2C (R/W) Bit [7:0]: * (Default 0)
Before requesting that the MVTX2603 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. When the MVTX2603 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the MVTX2603 does not start and pin CHECKSUM_OK is set to zero. The checksum formula is: FF
13.8 13.8.1
* *
I2C register = 0
I=0
Group 7 Address Port Mirroring Group MIRROR1_SRC - Port Mirror source port
CPU Address: h700 Accessed by serial interface (R/W) (Default 7F) 7 6 5 I/O Bit [4:0]: Bit [5]: Bit [7]: * * * * 4 Src Port Select 0
Source port to be mirrored. Use illegal port number to disable mirroring 1 - select ingress data 0 - select egress data Must be `1'
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MVTX2603
13.8.2
* *
Data Sheet
MIRROR1_DEST - Port Mirror destination
CPU Address: h701 Accessed by serial interface (R/W) (Default 17) 7 5 4 Dest Port Select Bit [4:0]: * Port Mirror Destination 0
13.8.3
* *
MIRROR2_SRC - Port Mirror source port
CPU Address: h702 Accessed by serial interface (R/W) (Default FF) 7 6 5 I/O Bit [4:0]: Bit [5]: Bit [7] * * * * 4 Src Port Select 0
Source port to be mirrored. Use illegal port number to disable mirroring 1 - select ingress data 0 - select egress data Must be 1
13.8.4
* *
MIRROR2_DEST - Port Mirror destination
CPU Address: h703 Accessed by serial interface (R/W) (Default 00) 7 5 4 Dest Port Select Bit [4:0]: * Port Mirror Destination 0
13.9 13.9.1
* *
Group F Address CPU Access Group GCR-Global Control Register
CPU Address: hF00 Accessed by serial interface. (R/W) 7 4 3 Reset Bit [0]: Bit[1]: * * * * 2 Bist 1 SR 0 SC
Store configuration (Default = 0) Write `1' followed by `0' to store configuration into external EEPROM Store configuration and reset (Default = 0) Write `1' to store configuration into external EEPROM and reset chip
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Data Sheet
Bit[2]: * * * * *
MVTX2603
Start BIST (Default = 0) Write `1' followed by `0' to start the device's built-in self-test. The result is found in the DCR register. Soft Reset (Default = 0) Write `1' to reset chip Reserved.
Bit[3]: Bit[7:4]:
13.9.2
* *
DCR-Device Status and Signature Register
CPU Address: hF01 Accessed by serial interface. (RO) 7 Revision Bit [0]: Bit[1]: Bit[2]: Bit[3]: Bit[5:4]: Bit [7:6]: * * * * * * * * * * * * * 6 5 Signature 4 3 RE 2 BinP 1 BR 0 BW
1: Busy writing configuration to I2C 0: Not busy writing configuration to I2C 1: Busy reading configuration from I2C 0: Not busy reading configuration from I2C 1: BIST in progress 0: BIST not running 1: RAM Error 0: RAM OK Device Signature 01: MVTX2603 device Revision 00: Initial Silicon 01: XA1 Silicon
13.9.3
* *
DCR1-Giga port status
CPU Address: hF02 Accessed by serial interface (RO) 7 CIC Bit [1:0]: * * * * * Giga port 0 strap option 00 - 100Mb MII mode 01 - 2G mode 10 - GMII 11 - PCS 6 4 3 2 GIGA1 1 GIGA0 0
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MVTX2603
Bit[3:2] * * * * * * Giga port 1 strap option 00 - 100Mb MII mode 01 - 2G mode 10 - GMII 11 - PCS Chip initialization completed
Data Sheet
Bit [7]
13.9.4
* *
DPST - Device Port Status Register
CPU Address: hF03 Accessed by serial interface (R/W) Bit[4:0]: * Read back index register. This is used for selecting what to read back from DTST. (Default 00)
5'b00000 - Port 0 Operating mode and Negotiation status 5'b00001 - Port 1 Operating mode/Neg status 5'b00010 - Port 2 Operating mode/Neg status 5'b00011 - Port 3 Operating mode/Neg status 5'b00100 - Port 4 Operating mode/Neg status 5'b00101 - Port 5 Operating mode/Neg status 5'b00110 - Port 6 Operating mode/Neg status 5'b00111 - Port 7 Operating mode/Neg status 5'b01000 - Port 8 Operating mode/Neg status 5'b01001 - Port 9 Operating mode/Neg status 5'b01010 - Port 10 Operating mode/Neg status 5'b01011 - Port 11 Operating mode/Neg status 5'b01100 - Port 12 Operating mode/Neg status 5'b01101 - Port 13 Operating mode/Neg status 5'b01110 - Port 14 Operating mode/Neg status 5'b01111 - Port 15 Operating mode/Neg status 5'b10000 - Port 16 Operating mode/Neg status 5'b10001 - Port 17 Operating mode/Neg status 5'b10010 - Port 18 Operating mode/Neg status 5'b00011 - Port 19 Operating mode/Neg status 5'b10100 - Port 20 Operating mode/Neg status 5'b10101 - Port 21 Operating mode/Neg status 5'b10110 - Port 22 Operating mode/Neg status 5'b10111 - Port 23 Operating mode/Neg status 5'b11000 - Reserved 5'b11001 - Port 25 Operating mode/Neg status (Gigabit port 1) 5'b11010 - Port 26 Operating mode/Neg status (Gigabit port 2)
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Data Sheet
13.9.5
* * *
MVTX2603
DTST - Data read back register
CPU Address: hF04 Accessed by serial interface (RO) This register provides various internal information as selected in DPST bit[4:0]. Refer to the PHY Control Application Note. 7 MD 6 Info 5 Sig 4 Giga 3 Inkdn 2 FE 1 Fdpx 0 FcEn
When bit is 1 * * * * * * * * Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] - Flow control enable - Full duplex port - Fast Ethernet port (if not gigabit port) - Link is down - Giga port - Signal detect (when PCS interface mode) - 2G signal detect (2G mode only) - Module detected (for hot swap purpose)
13.9.6
* *
PLLCR - PLL Control Register
CPU Address: hF05 Accessed by serial interface (RW) Bit[3] Bit[7] Must be '1' Selects strap option or LCLK/OECLK registers 0 - Strap option (default) 1 - LCLK/OECLK registers
13.9.7
* *
LCLK - LA_CLK delay from internal OE_CLK
CPU Address: hF06 Accessed by serial interface (RW) PD[12:10] 000b 001b 010b 011b 100b 101b 110b 111b LCLK 80h 40h 20h 10h 08h 04h 02h 01h Delay 8 Buffers Delay 7 Buffers Delay 6 Buffers Delay 5 Buffers Delay (Recommend) 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay
The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register.
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MVTX2603
13.9.8
* *
Data Sheet
OECLK - Internal OE_CLK delay from SCLK
CPU Address: hF07 Accessed by serial interface (RW)
The OE_CLK is used for generating the OE0 and OE1 signals. PD[15:13] 000b 001b 010b 011b 100b 101b 110b 111b OECLK 80h 40h 20h 10h 08h 04h 02h 01h Delay 8 Buffers Delay 7 Buffers Delay (Recommend) 6 Buffers Delay 5 Buffers Delay 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay
13.9.9
* * *
DA - DA Register
CPU Address: hFFF Accessed by CPU and serial interface (RO) Always return 8'h DA. Indicate the serial port connection is good.
13.10
TBI Registers
Two sets of TBI registers are used for configure the two Gigabit ports if they are operating in TBI mode. These TBI registers are located inside the switching chip and they are accessed through the MII command and MII data registers.
13.10.1 Control Register
* * MII Address: h00 Read/Write Bit [15] Reset PCS logic and all TBI registers 1 = Reset. 0 = Normal operation. Reserved. Must be programmed with "0". Speed selection (See bit 6 for complete details) * * * * * * * * Auto Negotiation Enable 1 = Enable auto-negotiation process. 0 = Disable auto-negotiation process (Default). Reserved. Must be programmed with "0" Restart Auto Negotiation. 1 = Restart auto-negotiation process. 0 = Normal operation (Default). Reserved.
Bit [14] Bit [13] Bit [12]
Bit [11:10] Bit [9]
Bit [8:7]
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Data Sheet
Bit [6] * Speed Selection
Bit[6][13] 1 1 = Reserved 0 =1000Mb/s (Default) 1 =100Mb/s 0 0 =10Mb/s
MVTX2603
Bit [5:0]
*
Reserved. Must be programmed with "0".
13.10.2 Status Register
* * MII Address: h01 Read Only Bit [15:9] Bit [8] Bit [7:6] Bit [5] * * * * * * * * * * Reserved. Always read back as "0". Reserved. Always read back as "1". Reserved. Always read back as "0". Auto-Negotiation Complete 1 = Auto-negotiation process completed. 0 = Auto-negotiation process not completed. Reserved. Always read back as "0" Reserved. Always read back as "1" Link Status 1 = Link is up. 0 = Link is down. Reserved. Always read back as "0". Reserved. Always read back as "1".
Bit [4] Bit [3] Bit [2]
Bit [1] Bit [0]
13.10.3 Advertisement Register
* * MII Address: h04 Read/Write Bit [15] Next Page 1 = Has next page capabilities. 0 = Do not has next page capabilities (Default). Reserved. Always read back as "0". Read Only. Remote Fault. Default is "0". * * * * * Reserved. Always read back as "0". Read Only. Pause. Default is "00" Half Duplex 1 = Support half duplex (Default). 0 = Do not support half duplex.
Bit [14] Bit [13:12] Bit [11:9] Bit [8:7] Bit [6]
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Bit [5] * * * * Full duplex 1 = Support full duplex (Default). 0 = Do not support full duplex. Reserved. Always read back as "0". Read Only.
Data Sheet
Bit [4:0]
13.10.4 Link Partner Ability Register
* * MII Address: h05 Read Only Bit [15] Next Page 1 = Has next page capabilities. 0 = Do not has next page capabilities. Acknowledge Remote Fault. * * * * * * * * * Reserved. Always read back as "0". Pause. Half Duplex 1 = Support half duplex. 0 = Do not support half duplex. Full duplex 1 = Support full duplex. 0 = Do not support full duplex. Reserved. Always read back as "0".
Bit [14] Bit [13:12] Bit [11:9] Bit [8:7] Bit [6]
Bit [5]
Bit [4:0]
13.10.5 Expansion Register
* * MII Address: h06 Read Only Bit [15:2] Bit [1] * * * * * Reserved. Always read back as "0". Page Received. 1 = A new page has been received. 0 = A new page has not been received. Reserved. Always read back as "0".
Bit [0]
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Data Sheet
13.10.6 Extended Status Register
* * MII Address: h15 Read Only Bit [15] * * * * * * * 1000 Full Duplex 1 = Support 1000 full duplex operation (Default). 0 = Do not support 1000 full duplex operation. 1000 Half Duplex 1 = Support 1000 half duplex operation (Default). 0 = Do not support 1000 half duplex operation. Reserved. Always read back as "0".
MVTX2603
Bit [14]
Bit [13:0]
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MVTX2603
14.0
14.1 14.1.1
1 A B 2 3
Data Sheet
BGA and Ball Signal Descriptions
BGA Views (Top-View) Encapsulated View
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDA 26 27 28 29 ST RO T STO BE UT7 D0 T STO TSTO UT8 UT 3
LA_D LA_D LA _D LA_D LA_D LA_A LA_O LA_A LA _A LA_A LA_A LA_D LA_D LA_D LA _D LA_D O E_C LA_C T RUN MIRR MIRR SCL 4 7 10 13 15 4 E0_ 8 13 16 19 33 36 39 42 45 LK0 LK0 K1 OR4 OR1
LA_D LA_D LA_D LA _D LA_D LA_D LA_A LA_O LA_A LA _A LA_A LA_A LA_D LA_D LA_D LA _D LA_D O E_C LA_C LA_D MIRR MIRR T RUN RESE 1 3 6 9 12 14 DSC_ E1_ 7 12 15 18 32 35 38 41 44 LK1 LK1 62 OR5 OR2 K2 RVED
C LA_C LA_D LA_D LA_D LA _D LA_D LA_A LA_O LA_W T_MO LA _A LA_A LA_A LA_A LA_D LA_D LA _D LA_D O E_C LA_C P_D T RUN MIRR MIRR AUT O T STO T STO TSTO TSTO LK 0 2 5 8 11 3 E_ E_ DE1 11 14 17 20 34 37 40 43 LK2 LK2 K0 OR3 OR0 FD UT 11 UT9 UT 4 UT 0 D AG N LA_D LA_D LA_D LA _D LA_D LA_D LA_D LA_D LA_A LA _A LA_W LA_D LA_D LA_D LA_D LA _D LA_D LA_D LA_D LA_D SCAN SCAN T STO T STO T STO T STO TSTO TSTO D 17 19 21 23 25 27 29 31 6 10 E0_ 49 51 53 55 57 59 61 63 47 C OL C LK UT 14 UT 13 UT 12 UT 10 UT 5 UT 1 SC AN SCAN T STO M26_ M26_ MOD LINK UT 15 CRS T XE R E M26_ M26_ M26_ MTX TXC L TXEN CLK K M26_ TXD1 4 M26_ TXD1 2 M26_ TXD1 0 VDD VDD VDD VDD M26_ T XD1 5 M26_ T XD1 3 M26_ T XD1 1 M26_ RXD1 5 M26_ RXD1 2 TSTO TSTO UT 6 UT 2 M26_ M26_ RXD RXCL V K M26_ M26_ RXER COL M26_ RX D1 4 M26_ RX D1 1
LA_D LA_D LA_D LA _D LA_D LA_D LA_D LA_D LA_A LA _A LA_W LA_D LA_D LA_D LA_D LA _D LA_D LA_D RESE LA_D E SC LK 16 18 20 22 24 26 28 30 5 9 E1_ 48 50 52 54 56 58 60 RVED 46 F G AVC C RESI SC AN LB_D LB_D N_ EN 63 62 VDD VDD 33 33 VDD 33 VDD VDD 33 33
RE SE LB_C LB_D LB_D LB_D T OUT LK 47 61 60 _
LB_D LB_D LB_D LB_D LB_D H 46 45 44 59 58 J LB_D LB_D LB_D LB_D LB_D 43 42 41 57 56 K LB_D LB_D LB_D LB_D LB_D 40 39 38 55 54 L LB_D LB_D LB_D LB_D LB_D 37 36 35 53 52 M N P LB_D LB_D LB_D LB_D LB_D 34 33 32 51 50 LB_A LB_A LB_A LB_D LB_D V DD 18 19 20 49 48 33 LB_A LB_A LB_A LB_W LB_ V DD 15 16 17 E0_ WE1_ 33 VDD VDD VSS VSS VSS VSS VSS VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD
M26_ RXD1 3 M26 M 2 6 _ R X D_ 1 RXD9 0
M26_ M26_ M26_ M26_ M26_ TXD9 T XD8 RXD6 RXD7 RX D8 M26_ M26_ M26_ M26_ M26_ TXD4 T XD6 RXD3 RXD4 RX D5 M26_ M26_ M26_ M26_ M26_ TXD7 T XD5 RXD0 RXD1 RX D2 VDD M26_ M26_ 33 T XD2 T XD3 VDD M26_ M26_ 33 T XD0 T XD1 VDD M25_ M25_ 33 CRS T XE R GRE F _CLK 1 GRE F MDIO _CLK 0 MDC M_CL K
R LB_A LB_A LB_A LB_A LB_A V DD 10 11 12 13 14 33 T LB_A LB_A LB_A LB_A LB_A V DD 5 6 7 8 9 33 LB_O LB_O T_MO LB_D LB_D V DD U E0_ E1_ DE0 31 30 33 V W Y LB_A LB_O LB_W LB_D LB_D DSC_ E_ E_ 29 28 LB_D LB_A LB_A LB_D LB_D 15 3 4 27 26 LB_D LB_D LB_D LB_D LB_D 14 13 12 25 24
M25 _ M25 V D D T X C _ M 2 5 _ M 2 5X M 2 5 _ R X C _ L MT RXD L 33 TXEN K CLK V K M25_ VDD 33 T XD1 4 M25_ TXD1 2 M25_ TXD1 0 M25_ T XD1 5 M25_ T XD1 3 M25_ T XD1 1 M25_ RXD1 5 M25_ RXD1 2 M25_ M25_ RXER COL M25_ RX D1 4 M25_ RX D1 1
M25_ RXD1 3 M25_ M25_ RXD1 RXD9 0
VDD VDD
VDD VDD
M25_ M25_ M25_ M25_ M25_ RXD 6 T XD8 T XD9 RXD7 RX D8 M25_ M25_ M25_ M25_ M25_ TXD6 T XD7 RXD3 RXD4 RX D5 M25_ M25_ M25_ M25_ M25_ TXD4 T XD5 RXD0 RXD1 RX D2 M25_ M25_ M23_ M23_ M23_ TXD2 T XD3 C RS RXD0 RX D1
A LB_D LB_D LB_D LB_D LB_D 11 10 9 23 22 A A LB_D LB_D LB_D LB_D LB_D 8 7 6 21 20 B A LB_D LB_D LB_D LB_D LB_D 5 4 3 19 18 C A LB_D LB_D LB_D LB_D LB_D 2 1 0 17 16 D VDD VDD 33 33 VDD 33 VDD VDD 33 33
M25_ M25_ M23_ M23_ M23_ TXD0 T XD1 T XD1 T XD0 T XEN
A M0_T M0_T M0_T M3_T M3_T M3_R M5_T M5_T M5_R M8_T M8_T M8_R M10_ M10_ M10_ M13_ M16_ M15_ M16_ M15_ M15_ M18_ M18_ M18_ M20_ M20_ M20_ M22_ E XEN XD0 XD1 X D1 X EN XD0 XD1 XEN XD0 X D1 X EN XD0 TXD1 TXEN RXD0 T XD1 TXD0 TXD1 RXD1 TXEN RXD0 T XD1 T XEN RXD 0 TXD1 TXEN RXD0 RXD1 AF M0_R M0_R M0_C M3_T M3_ C M3_R M5_T M5_C M5_R M8_T M8_ C M8_R M10_ M10_ M10_ M13_ M13_ M13_ M14_ M16R M15_ M17_ M17_ M18_ M20_ M20_ M20_ M22_ M22_ XD1 XD0 RS XD0 RS XD1 XD0 RS XD1 XD0 RS XD1 TXD0 CRS RXD1 T XD0 CRS RXD 1 CRS XD0 RXD1 RXD0 CRS RXD 1 TXD0 CRS RXD1 RXD0 CRS
A M1_T M1_T M1_T M2_T M2_ C M4_T M4_C M6_T M6_C M7_T M7_ C M9_T M9_C M11_ M11_ M12_ M12_ M14_ M15_ M16_ M16_ M18_ M18_ M19_ M19_ M21_ M21_ M22_ M22_ RS XD1 RS XD1 RS XD1 RS XD1 RS T XD1 C RS T XD1 CRS TXD1 TXD0 T XD1 C RS T XD0 CRS TXD1 CRS T XD1 C RS T XEN TXD0 G XEN XD0 XD1 XD1 A H AJ 1 2 M1_R M1_C M2_T M2_ R M4_T M4_R M6_T M6_R M7_T M7_ R M9_T M9_R M11_ M11_ M12_ M12_ M14_ M14_ M13_ M15_ M17_ M17_ M19_ M19_ M21_ M21_ M22_ XD0 RS X D0 XD 0 XD0 XD0 XD0 XD0 X D0 XD 0 XD0 XD0 T XD0 RXD0 T XD0 RX D0 TXD0 RXD0 RXD0 C RS T XD0 RX D1 TXD0 RXD0 T XD0 RXD0 T XD1 M1_R M2_T M2_ R M4_T M4_R M6_T M6_R M7_T M7_ R M9_T M9_R M11_ M11_ M12_ M12_ M14_ M14_ M16_ M13_ M17_ M17_ M19_ M19_ M21_ M21_ XD1 X EN XD 1 XEN XD1 XEN XD1 XEN XD 1 XEN XD1 TXEN RXD1 T XEN RX D1 TXEN RXD1 TXEN T XEN T XEN TXD1 TXEN RXD1 TXEN RXD1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Figure 18 - BGA View
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Zarlink Semiconductor Inc.
Data Sheet
14.1.2 Power and Ground Distribution
MVTX2603
The following figure provides an encapsulated view of the power and ground distribution
1 A B C D 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
LA_ D LA_ D LA_ D LA_ D LA_ D LA_ A LA_ O LA_ A LA_ A LA_ A LA_ A LA_ D LA_ D LA_ D LA_ D LA_ D R ESE R ES E TR UN MIR R MIR R S C L 4 7 10 13 15 4 E0 8 13 16 19 33 36 39 42 4 5 R VED R VED K1 OR 4 OR 1
SDA STR O TS TO B E UT7 D0 TS TO TSTO UT8 UT3
LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ A LA_ O LA_ A LA_ A LA_ A LA_ A LA_ D LA_ D LA_ D LA_ D LA_ D R ESE R ES E LA_ D MIR R MIR R TR UN R ES E 1 3 6 9 12 1 4 DSC E1 7 12 15 18 32 35 38 41 4 4 R VED R VED 6 2 OR 5 OR 2 K2 R VED
LA_ C LA_ D LA_ D LA_ D LA_ D LA_ D LA_ A LA_ O LA W T_ MO LA_ A LA_ A LA_ A LA_ A LA_ D LA_ D LA_ D LA_ D R ESE R ES E R ESE TR UN MIR R MIR R AUTO TS TO TS TO TSTO TS TO E_ DE1 11 14 17 20 34 37 40 4 3 R VED R VED R VED K0 OR 3 OR 0 FD UT1 1 UT9 UT4 UT0 LK 0 2 5 8 11 3 E_ AGN LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ A LA_ A LA W LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D S C AN S C AN TS TO TSTO TS TO TS TO TSTO TS TO E0 49 51 53 55 57 59 61 63 47 C OL C LK UT1 4 UT1 3 UT1 2 UT1 0 UT5 UT1 D 17 19 21 23 25 27 29 31 6 10 S C AN TS TO M2 6 _ M2 6 _ SC AN TSTO TS TO LINK UT1 5 C R S TXER MOD UT6 UT2 E M2 6 _ M2 6 _ M2 6 _ M2 6 _ M2 6 _ TXC L TXEN MTX R XD R XC L K C LK V K M2 6 _ M2 6 _ M2 6 _ M2 6 _ M2 6 _ TXD1 TXD1 R XD1 R XER C OL 4 5 5 M2 6 _ M2 6 _ M2 6 _ M2 6 _ M2 6 _ TXD1 TXD1 R XD1 R XD1 R XD1 2 3 2 3 4 M2 6 _ M2 6 _ M2 6 _ M2 6 _ M2 6 _ TXD1 TXD1 R XD9 R XD1 R XD1 0 1 0 1 M2 6 _ M2 6 _ M2 6 _ M2 6 _ M2 6 _ TXD9 TXD8 R XD6 R XD7 R XD8 M2 6 _ M2 6 _ M2 6 _ M2 6 _ M2 6 _ TXD4 TXD6 R XD3 R XD4 R XD5 VDD VDD VS S VS S VS S VS S VS S VDD VDD VS S VS S VSS VSS VSS VSS VSS VSS VSS VS S VS S VS S VS S VS S VS S VS S VSS VSS VSS VSS VSS VSS VSS VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD M2 6 _ M2 6 _ M2 6 _ M2 6 _ M2 6 _ TXD7 TXD5 R XD0 R XD1 R XD2 VDD M2 6 _ M2 6 _ D_ C O D_ C O GR EF 3 3 TXD2 TXD3 NF IG NFIG _ C LK 1 0 1 GR EF VDD M2 6 _ M2 6 _ MDIO _ C LK 3 3 TXD0 TXD1 0 VDD M2 5 _ M2 5 _ 33 C R S TXER VDD M2 5 _ M2 5 _ 3 3 TXC L TXEN K VDD M2 5 _ M2 5 _ 3 3 TXD1 TXD1 4 5 M2 5 _ M2 5 _ TXD1 TXD1 2 3 M2 5 _ M2 5 _ TXD1 TXD1 0 1 MDC M_ C L K M2 5 _ M2 5 _ M2 5 _ MTX R XD R XC L C LK V K M2 5 _ M2 5 _ M2 5 _ R XD1 R XER C OL 5 M2 5 _ M2 5 _ M2 5 _ R XD1 R XD1 R XD1 2 3 4 M2 5 _ M2 5 _ M2 5 _ R XD1 R XD1 R XD9 0 1
LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ A LA_ A LA W LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D LA_ D R ES E LA_ D E SC LK 1 6 18 20 22 24 26 28 30 5 9 E1 48 50 52 54 56 58 6 0 R VED 4 6 F AVC R ESI S C AN LB _ D LB _ D C N_ EN 63 62 VDD VDD VDD VDD VDD 33 33 33 33 33
LB _ C R ESE LB _ D LB _ D LB _ D G LK TOUT 4 7 61 60 _ H LB _ D LB _ D LB _ D LB _ D LB _ D 46 45 44 59 58
LB _ D LB _ D LB _ D LB _ D LB _ D J 43 42 41 57 56 K LB _ D LB _ D LB _ D LB _ D LB _ D 40 39 38 55 54 VDD VDD VDD VDD
L LB _ D LB _ D LB _ D LB _ D LB _ D 37 36 35 53 52 M N P LB _ D LB _ D LB _ D LB _ D LB _ D 34 33 32 51 50 LB _ A LB _ A LB _ A LB _ D LB _ D VDD 18 19 20 49 48 33 LB _ A LB _ A LB _ A LB W LB _ E0 W E1 15 16 17 VDD 33
LB _ A LB _ A LB _ A LB _ A LB _ A VDD R 10 11 12 13 14 33 T U LB _ A LB _ A LB _ A LB _ A LB _ A VDD 5 6 7 8 9 33 LB _ O LB _ O T_ MO LB _ D LB _ D VDD E0 E1 DE0 31 30 33
LB _ A LB _ O LB W LB _ D LB _ D V DS C E_ 29 28 E_ LB _ D LB _ A LB _ A LB _ D LB _ D W 15 3 4 27 26 Y A A LB _ D LB _ D LB _ D LB _ D LB _ D 14 13 12 25 24 LB _ D LB _ D LB _ D LB _ D LB _ D 11 10 9 23 22
VDD VDD
VDD VDD
M2 5 _ M2 5 _ M2 5 _ M2 5 _ M2 5 _ R XD6 TXD8 TXD9 R XD7 R XD8 M2 5 _ M2 5 _ M2 5 _ M2 5 _ M2 5 _ TXD6 TXD7 R XD3 R XD4 R XD5 M2 5 _ M2 5 _ M2 5 _ M2 5 _ M2 5 _ TXD4 TXD5 R XD0 R XD1 R XD2 M2 5 _ M2 5 _ M2 3 _ M2 3 _ M2 3 _ TXD2 TXD3 C R S R XD0 R XD1
A LB _ D LB _ D LB _ D LB _ D LB _ D 8 7 6 21 20 B A LB _ D LB _ D LB _ D LB _ D LB _ D 5 4 3 19 18 C A D LB _ D LB _ D LB _ D LB _ D LB _ D 2 1 0 17 16 VDD VDD VDD VDD VDD 33 33 33 33 33
M2 5 _ M2 5 _ M2 3 _ M2 3 _ M2 3 _ TXD0 TXD1 TXD1 TXD0 TXEN
M0 _ T M0 _ T M0 _ T M3 _ T M3 _ T M3 _ R M5 _ T M5 _ T M5 _ R M8 _ T M8 _ T M8 _ R M1 0 _ M1 0 _ M1 0 _ M1 3 _ M1 6 _ M1 5 _ M1 6 _ M1 5 _ M1 5 _ M1 8 _ M1 8 _ M1 8 _ M2 0 _ M2 0 _ M2 0 _ M2 2 _ A XEN XD0 XD1 XD1 XEN XD0 XD1 XEN XD0 XD1 XEN XD0 TXD1 TXEN R XD0 TXD1 TXD0 TXD1 R XD1 TXEN R XD0 TXD1 TXEN R XD0 TXD1 TXEN R XD0 R XD1 E M0 _ R M0 _ R M0 _ C M3 _ T M3 _ C M3 _ R M5 _ T M5 _ C M5 _ R M8 _ T M8 _ C M8 _ R M1 0 _ M1 0 _ M1 0 _ M1 3 _ M1 3 _ M1 3 _ M1 4 _ M1 6 R M1 5 _ M1 7 _ M1 7 _ M1 8 _ M2 0 _ M2 0 _ M2 0 _ M2 2 _ M2 2 _ AF XD1 XD0 R S XD0 R S XD1 XD0 R S XD1 XD0 R S XD1 TXD0 C R S R XD1 TXD0 C R S R XD1 C R S XD0 R XD1 R XD0 C R S R XD1 TXD0 C R S R XD1 R XD0 C R S A M1 _ T M1 _ T M1 _ T M2 _ T M2 _ C M4 _ T M4 _ C M6 _ T M6 _ C M7 _ T M7 _ C M9 _ T M9 _ C M1 1 _ M1 1 _ M1 2 _ M1 2 _ M1 4 _ M1 5 _ M1 6 _ M1 6 _ M1 8 _ M1 8 _ M1 9 _ M1 9 _ M2 1 _ M2 1 _ M2 2 _ M2 2 _ R S XD1 R S XD1 R S XD1 R S XD1 R S TXD1 C R S TXD1 C R S TXD1 TXD0 TXD1 C R S TXD0 C R S TXD1 C R S TXD1 C R S TXEN TXD0 G XEN XD0 XD1 XD1 A H AJ 1 2 M1 _ R M1 _ C M2 _ T M2 _ R M4 _ T M4 _ R M6 _ T M6 _ R M7 _ T M7 _ R M9 _ T M9 _ R M1 1 _ M1 1 _ M1 2 _ M1 2 _ M1 4 _ M1 4 _ M1 3 _ M1 5 _ M1 7 _ M1 7 _ M1 9 _ M1 9 _ M2 1 _ M2 1 _ M2 2 _ XD0 R S XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 TXD0 R XD0 TXD0 R XD0 TXD0 R XD0 R XD0 C R S TXD0 R XD1 TXD0 R XD0 TXD0 R XD0 TXD1 M1 _ R M2 _ T M2 _ R M4 _ T M4 _ R M6 _ T M6 _ R M7 _ T M7 _ R M9 _ T M9 _ R M1 1 _ M1 1 _ M1 2 _ M1 2 _ M1 4 _ M1 4 _ M1 6 _ M1 3 _ M1 7 _ M1 7 _ M1 9 _ M1 9 _ M2 1 _ M2 1 _ XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 TXEN R XD1 TXEN R XD1 TXEN R XD1 TXEN TXEN TXEN TXD1 TXEN R XD1 TXEN R XD1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Figure 19 - Power and Ground Distribution View
Zarlink Semiconductor Inc.
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MVTX2603
14.2 Ball - Signal Descriptions
Data Sheet
All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive.
14.2.1
Ball Signal Descriptions
Ball Signal Descriptions Table
Ball No(s) Symbol I/O Description
I2C Interface Note: Use I2C and Serial control interface to configure the system A24 A25 Serial Control Interface A26 B26 C25 Frame Buffer Interface D20, B21, D19, E19,D18, E18, D17, E17, D16, E16, D15, E15, D14, E14, D13, E13, D21, E21, A18, B18, C18, A17, B17, C17, A16, B16, C16, A15, B15, C15, A14, B14, D9, E9, D8, E8, D7, E7, D6, E6, D5, E5, D4, E4, D3, E3, D2, E2, A7, B7, A6, B6, C6, A5, B5, C5, A4, B4, C4, A3, B3, C3, B2, C2 C14, A13, B13, C13, A12, B12, C12, A11, B11, C11, D11, E11, A10, B10, D10, E10, A8, C7 B8 C1 C9 D12 LA_D[63:0] I/O-TS with pull up Frame Bank A- Data Bit [63:0] STROBE D0 AUTOFD Input with weak internal pull up Input Output with pull up Serial Strobe Pin Serial Data Input Serial Data Output (AutoFD) SCL SDA Output I/O-TS with pull up I2C Data Clock I2C Data I/O
LA_A[20:3]
Output
Frame Bank A - Address Bit [20:3]
LA_ADSC# LA_CLK LA_WE# LA_WE0#
Output with pull up Output Output with pull up Output with pull up
Frame Bank Control
A
Address Status
Frame Bank A Clock Input Frame Bank A Write Chip Select for one layer SRAM application Frame Bank A Write Chip Select for lower layer of two layers SRAM application Frame Bank A Write Chip Select for upper layer of two layers SRAM application Frame Bank A Read Chip Select for one layer SRAM application
E12
LA_WE1#
Output with pull up
C8
LA_OE#
Output with pull up
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Zarlink Semiconductor Inc.
Data Sheet Ball Signal Descriptions Table (continued)
A9 LA_OE0# Output with pull up
MVTX2603
Frame Bank A Read Chip Select for lower layer of two layers SRAM application Frame Bank A Read Chip Select for upper layer of two layers SRAM application Frame Bank B- Data Bit [63:0]
B9
LA_OE1#
Output with pull up
F4, F5, G4, G5, H4, H5, J4, J5, K4, K5, L4, L5, M4, M5, N4, N5, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, M1, M2, M3, U4, U5, V4, V5, W4, W5, Y4, Y5, AA4, AA5, AB4, AB5, AC4, AC5, AD4, AD5, W1, Y1, Y2, Y3, AA1, AA2, AA3, AB1, AB2, AB3, AC1, AC2, AC3, AD1, AD2, AD3 N3, N2, N1, P3, P2, P1, R5, R4, R3, R2, R1, T5, T4, T3, T2, T1, W3, W2 V1 G1 V3 P4
LB_D[63:0]
I/O-TS with pull up.
LB_A[20:3]
Output
Frame Bank B - Address Bit [20:3]
LB_ADSC# LB_CLK LB_WE# LB_WE0#
Output with pull up Output Output with pull up Output with pull up
Frame Bank Control
B
Address Status
Frame Bank B Clock Input Frame Bank B Write Chip Select for one layer SRAM application Frame Bank B Write Chip Select for lower layer of two layers SRAM application Frame Bank B Write Chip Select for upper layer of two layers SRAM application Frame Bank B Read Chip Select for one layer SRAM application Frame Bank B Write Chip Select for lower layer of two layers SRAM application Frame Bank B Write Chip Select for upper layer of two layers SRAM application
P5
LB_WE1#
Output with pull up
V2 U1
LB_OE# LB_OE0#
Output with pull up Output with pull up
U2
LB_OE1#
Output with pull up
Fast Ethernet Access Ports [23:0] RMII R28 P28 R29 M_MDC M_MDIO M_CLKI Output I/O-TS with pull up Input MII Management Data Clock - (Common for all MII Ports [23:0]) MII Management Data I/O - (Common for all MII Ports -[23:0])) Reference Input Clock
Zarlink Semiconductor Inc.
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MVTX2603
Ball Signal Descriptions Table (continued)
AC29, AE28, AJ27, AF27, AJ25, AF24, AH23, AE19, AF21, AJ19, AF18, AJ17, AJ15, AF15, AJ13, AF12, AJ11, AJ9, AF9, AJ7, AF6, AJ5, AJ3, AF1 AC28, AF28, AH27, AE27, AH25, AE24, AF22, AF20, AE21, AH19, AH20, AH17, AH15, AE15, AH13, AE12, AH11, AH9, AE9, AH7, AE6, AH5, AH2, AF2 AC27, AF29, AG27, AF26, AG25, AG23, AF23, AG21, AH21, AF19, AF17, AG17, AG15, AF14, AG13, AF11, AG11, AG9, AF8, AG7, AF5, AG5, AH3, AF3 AD29, AG28, AJ26, AE26, AJ24, AE23, AJ22, AJ20, AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1 AD27, AH28, AG26, AE25, AG24, AE22, AJ23, AG20, AE18, AG18, AE16, AG16, AG14, AE13, AG12, AE10, AG10, AG8, AE7, AG6, AE4, AG4, AG3, AE3 AD28, AG29, AH26, AF25, AH24, AG22, AH22, AE17, AG19, AH18, AF16, AH16, AH14, AF13, AH12, AF10, AH10, AH8, AF7, AH6, AF4, AH4, AG2, AE2 M[23:0]_RXD[1] Input with weak internal pull up resistors.
Data Sheet
Ports [23:0] - Receive Data Bit [1]
M[23:0]_RXD[0]
Input with weak internal pull up resistors
Ports [23:0] - Receive Data Bit [0]
M[23:0]_CRS_DV
Input with weak internal pull down resistors.
Ports [23:0] - Carrier Sense and Receive Data Valid
M[23:0]_TXEN
I/O- TS with pull up, slew
Ports [23:0] - Transmit Enable Strap option for RMII/GPSI
M[23:0]_TXD[1]
Output, slew
Ports [23:0] - Transmit Data Bit [1]
M[23:0]_TXD[0]
Output, slew
Ports [23:0] - Transmit Data Bit [0]
GMII/TBI Gigabit Ethernet Access Ports 0 & 1 U26, U25, V26, V25, W26, W25, Y27, Y26, AA26, AA25, AB26, AB25, AC26, AC25, AD26, AD25 T28 U28 R25 U29 T29 M25_TXD[15:0] Output
Transmit Data Bit [15:0] [7:0] - GMII [9:0] - TBI [15:0] - 2G
Receive Data Valid Receive Error Carrier Sense Collision Detected Receive Clock
M25_RX_DV M25_RX_ER M25_CRS M25_COL M25_RXCLK
Input w/ pull down Input w/ pull up Input w/ pull down Input w/ pull up Input w/ pull up
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Zarlink Semiconductor Inc.
Data Sheet Ball Signal Descriptions Table (continued)
U27, V29, V28, V27, W29, W28, W27, Y29, Y28, Y25, AA29, AA28, AA27, AB29, AB28, AB27 T26 R26 T25 P29 G26, G25, H26, H25, J26, J25, K25, K26, M25, L26, M26, L25, N26, N25, P26, P25 M25_RXD[15:0] Input w/ pull up
MVTX2603
Receive Data Bit [15:0] [7:0] - GMII [9:0] - TBI [15:0] - 2G
M25_TX_EN M25_TX_ER M25_ TXCLK GREF_CLK0 M26_TXD[15:0]
Output w/ pull up Output w/ pull up
Output Input w/ pull up Output
Transmit Data Enable Transmit Error Gigabit Transmit Clock Gigabit Reference Clock
Transmit Data Bit [15:0] [7:0] - GMII [9:0] - TBI [15:0] - 2G
F28 G28 E25 G29 F29 G27,H29, H28, H27, J29, J28, J27, K29, K28, K27, L29, L28, L27, M29, M28, M27
M26_RX_DV M26_RX_ER M26_CRS M26_COL M26_RXCLK M26_RXD[15:0]
Input w/ pull down Input w/ pull up Input w/ pull down Input w/ pull up Input w/ pull up Input w/ pull up
Receive Data Valid Receive Error Carrier Sense Collision Detected Receive Clock
Receive Data Bit [15:0] [7:0] - GMII [9:0] - TBI [15:0] - 2G
F26 E26 F25 N29 LED Interface C29 D29 E29 B28 C28
M26_TX_EN M26_TX_ER M26_ TXCLK GREF_CLK1
Output w/ pull up Output w/ pull up Output Input w/ pull up
Transmit Data Enable Transmit Error Gigabit Transmit Clock Gigabit Reference Clock
LED_CLK/TSTOU T0 LED_SYN/TSTO UT1 LED_BIT/TSTOU T2 G1_RXTX#/TSTO UT3 G1_DPCOL#/TST OUT4
I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up
LED Serial Interface Output Clock LED Output Data Stream Envelope LED Serial Data Output Stream LED for Gigabit port 1 (receive + transmit) LED for Gigabit port 1 (full duplex + collision)
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MVTX2603
Ball Signal Descriptions Table (continued)
D28 E28 A27 B27 C27 D27 C26 D26 D25 D24 E24 Trunk Enable C22 A21 B24 Test Facility U3 T_MODE0 I/O-TS TRUNK0 TRUNK1 TRUNK2 Input w/ weak internal pull down resistors Input w/ weak internal pull down resistors Input w/ weak internal pull down resistors Trunk Port Enable Trunk Port Enable Trunk Port Enable G1_LINK#/TSTO UT5 G2_RXTX#/TSTO UT6 G2_DPCOL#/TST OUT7 G2_LINK#/TSTO UT8 INIT_DONE/TST OUT9 INIT_START/TST OUT10 CHECKSUM_OK/ TSTOUT11 FCB_ERR/TSTO UT12 MCT_ERR/TSTO UT13 BIST_IN_PRC/TS TOUT14 BIST_DONE/TST OUT15 I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up LED for Gigabit port 1
Data Sheet
LED for Gigabit port 2 (receive + transmit) LED for Gigabit port 2 (full duplex + collision) LED for Gigabit port 2 System start operation Start initialization EEPROM read OK FCB memory self test fail MCT memory self test fail Processing memory self test Memory self test done
Test Pin - Set Mode upon Reset, and provides NAND Tree test output during test mode (Pull Up)
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Zarlink Semiconductor Inc.
Data Sheet Ball Signal Descriptions Table (continued)
C10 T_MODE1 I/O-TS
MVTX2603
Test Pin - Set Mode upon Reset, and provides NAND Tree test output during test mode (Pull Up) T_MODE1 0 0 1 1 T_MODE0 0 NandTree 1 Reserved 0 Reserved 1 Regular operation T_MODE0 and T_MODE1 are used for manufacturing tests. The signals should both be set to 1 for regular operation.
F3
SCAN_EN
Input with pull down
Scan Enable 0 - Normal mode (unconnected)
E27
SCANMODE
Input with pull down
1 - Enables Test mode. 0 - Normal mode (unconnected)
System Clock, Power, and Ground Pins E1 K12, K13, K17,K18 M10, N10, M20, N20, U10, V10, U20, V20, Y12, Y13, Y17, Y18 F13, F14, F15, F16, F17, N6, P6, R6, T6, U6, N24, P24, R24, T24, U24, AD13, AD14, AD15, AD16, AD17 M12, M13, M14, M15, M16, M17, M18, N12, N13, N14, N15, N16, N17, N18, P12, P13, P14, P15, P16, P17, P18, R12, R13, R14, R15, R16, R17, R18, T12, T13, T14, T15, T16, T17, T18, U12, U13, U14, U15, U16, U17, U18, V12, V13, V14, V15, V16, V17, V18, F1 D1 MISC D22 D23 SCANCOL SCANCLK Input Input/ output Scans the Collision signal of Home PHY Clock for scanning Home PHY collision and link SCLK VDD Input Power System Clock at 100 MHz +2.5 Volt DC Supply
VDD33
Power
+3.3 Volt DC Supply
VSS
Power Ground
Ground
AVCC AGND
Analog Power Analog Ground
Analog +2.5 Volt DC Supply Analog Ground
Zarlink Semiconductor Inc.
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MVTX2603
Ball Signal Descriptions Table (continued)
E23 F2 G2 E20, B25 SCANLINK RESIN# RESETOUT_ Reserved Input Input Output I/O-TS
Data Sheet
Link up signal from Home PHY Reset Input Reset PHY
Reserved Pins. Leave unconnected.
Bootstrap Pins (Default= pull up, 1= pull up 0= pull down) After reset TSTOUT0 to TSTOUT15 are used by the LED interface. C29 TSTOUT0 Default: Active High (1) GIGA Link polarity 0 - Active low 1 - Active high D29 TSTOUT1 Default: Enable (1) RMII MAC Power Saving Enable 0 - No power saving 1 - Power saving E29 TSTOUT2
Default: Enable (1) Recommend disable (0) with pull-down
Giga Half Duplex Support 0 - Disable 1 - Enable
Reserved
C28, B28 C28
TSTOUT[4:3] TSTOUT4 Default: SBRAM (1)
Memory is SBRAM/ZBT 0 - ZBT 1 - Pipeline SBRAM
D28
TSTOUT5
Default: SCLK (1)
Scan Speed 0 - 1/4 SCLK(HPNA) 1 - SCLK
E28 A27
TSTOUT6 TSTOUT7 Default: 128K x 32 or 128K x 64 (1)
Reserved Memory Size 0 - 256K x 32 or 256K x 64 (4M total) 1 - 128K x 32 or 128K x 64 (2M total)
B27
TSTOUT8
Default: Not Installed (1)
EEPROM Installed 0 - EEPROM installed 1 - EEPROM not installed
C27
TSTOUT9
Default: MCT enable (1)
aging
MCT Aging 0 - MCT aging disable 1 - MCT aging enable
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Zarlink Semiconductor Inc.
Data Sheet Ball Signal Descriptions Table (continued)
D27 TSTOUT10 Default: FCB enable (1) aging FCB Aging
MVTX2603
0 - FCB aging disable 1 - FCB aging enable C26 TSTOUT11 Default: Timeout reset enable (1) Timeout Reset 0 - Time out reset disable 1 - Time out reset enable. Issue reset if any state machine did not go back to idle for 5 Sec. D26 TSTOUT12 Default: Normal (1) Test Speed Up 0 - Enable test speed up. Do not use. 1 - Disable test speed up D25 TSTOUT13 Default: Single depth (1) FDB RAM depth (1 or 2 layers) 0 - Two layers 1 - One layer D24 E24 TSTOUT14 TSTOUT15 Default: operation Normal Reserved. SRAM Test Mode 0 - Enable test mode 1 - Normal operation T26, R26 G0_TXEN, G0_TXER Default: PCS Giga0 Mode: G0_TXEN G0_TXER 0 0 MII 0 1 2G 1 0 GMII 1 1 PCS F26, E26 G1_TXEN, G1_TXER Default: PCS Giga1 Mode: G1_TXEN G1_TXER 0 0 MII 0 1 2G 1 0 GMII 1 1 PCS AD29, AG28, AJ26, AE26, AJ24, AE23, AJ22, AJ20, AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1, C21 C19, B19, A19 M[23:0]_TXEN Default: RMII 0 - GPSI 1 - RMII
P_D OE_CLK[2:0]
Must be pulled-down Default: 111
Reserved. Must be pulled-down. Programmable delay for internal OE_CLK from SCLK input. The OE_CLK is used for generating the OE0 and OE1 signals Suggested value is 001.
Zarlink Semiconductor Inc.
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MVTX2603
Ball Signal Descriptions Table (continued)
C20, B20, A20 LA_CLK[2:0] Default: 111
Data Sheet
Programmable delay for LA_CLK and LB_CLK from internal OE_CLK. The LA_CLK and LB_CLK delay from SCLK is the sum of the delay programmed in here and the delay in P_D[15:13]. Suggested value is 011.
B22, A22, C23, B23, A23, C24
MIRROR[5:0]
Default: 111111
Dedicated Port Mirror Mode. The first 5 bits select the port to be mirrored. The last bit selects either ingress or egress data.
Notes: #= Input = In-ST = Output = Out-OD= I/O-TS = I/O-OD = Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver
14.3
Ball - Signal Name
Ball - Signal Name Table
Ball No. D20 B21 D19 E19 D18 E18 D17 E17 D16 E16 D15 E15 LA_D[63] LA_D[62] LA_D[61] LA_D[60] LA_D[59] LA_D[58] LA_D[57] LA_D[56] LA_D[55] LA_D[54] LA_D[53] LA_D[52] Signal Name Ball No. D3 E3 D2 E2 A7 B7 A6 B6 C6 A5 B5 C5 Signal Name LA_D[19] LA_D[18] LA_D[17] LA_D[16] LA_D[15] LA_D[14] LA_D[13] LA_D[12] LA_D[11] LA_D[10] LA_D[9] LA_D[8] Ball No. A9 B9 F4 F5 G4 G5 H4 H5 J4 J5 K4 K5 LA_OE0# LA_OE1# LB_D[63] LB_D[62] LB_D[61] LB_D[60] LB_D[59] LB_D[58] LB_D[57] LB_D[56] LB_D[55] LB_D[54] Signal Name
90
Zarlink Semiconductor Inc.
Data Sheet Ball - Signal Name Table (continued)
Ball No. D14 E14 D13 E13 D21 E21 A18 B18 C18 A17 B17 C17 A16 B16 C16 A15 B15 C15 A14 B14 D9 E9 D8 E8 D7 E7 D6 E6 D5 E5 LA_D[51] LA_D[50] LA_D[49] LA_D[48] LA_D[47] LA_D[46] LA_D[45] LA_D[44] LA_D[43] LA_D[42] LA_D[41] LA_D[40] LA_D[39] LA_D[38] LA_D[37] LA_D[36] LA_D[35] LA_D[34] LA_D[33] LA_D[32] LA_D[31] LA_D[30] LA_D[29] LA_D[28] LA_D[27] LA_D[26] LA_D[25] LA_D[24] LA_D[23] LA_D[22] Signal Name Ball No. A4 B4 C4 A3 B3 C3 B2 C2 C14 A13 B13 C13 A12 B12 C12 A11 B11 C11 D11 E11 A10 B10 D10 E10 A8 C7 B8 C1 C9 D12 Signal Name LA_D[7] LA_D[6] LA_D[5] LA_D[4] LA_D[3] LA_D[2] LA_D[1] LA_D[0] LA_A[20] LA_A[19] LA_A[18] LA_A[17] LA_A[16] LA_A[15] LA_A[14] LA_A[13] LA_A[12] LA_A[11] LA_A[10] LA_A[9] LA_A[8] LA_A[7] LA_A[6] LA_A[5] LA_A[4] LA_A[3] LA_ADSC# LA_CLK LA_WE# LA_WE0# Ball No. L4 L5 M4 M5 N4 N5 G3 H1 H2 H3 J1 J2 J3 K1 K2 K3 L1 L2 L3 M1 M2 M3 U4 U5 V4 V5 W4 W5 Y4 Y5 LB_D[53] LB_D[52] LB_D[51] LB_D[50] LB_D[49] LB_D[48] LB_D[47] LB_D[46] LB_D[45] LB_D[44] LB_D[43] LB_D[42] LB_D[41] LB_D[40] LB_D[39] LB_D[38] LB_D[37] LB_D[36] LB_D[35] LB_D[34] LB_D[33] LB_D[32] LB_D[31] LB_D[30] LB_D[29] LB_D[28] LB_D[27] LB_D[26] LB_D[25] LB_D[24]
MVTX2603
Signal Name
Zarlink Semiconductor Inc.
91
MVTX2603
Ball - Signal Name Table (continued)
Ball No. D4 E4 AB4 AB5 AC4 AC5 AD4 AD5 W1 Y1 Y2 Y3 AA1 AA2 AA3 AB1 AB2 AB3 AC1 AC2 AC3 AD1 AD2 AD3 N3 N2 N1 P3 P2 P1 LA_D[21] LA_D[20] LB_D[21] LB_D[20] LB_D[19] LB_D[18] LB_D[17] LB_D[16] LB_D[15] LB_D[14] LB_D[13] LB_D[12] LB_D[11] LB_D[10] LB_D[9] LB_D[8] LB_D[7] LB_D[6] LB_D[5] LB_D[4] LB_D[3] LB_D[2] LB_D[1] LB_D[0] LB_A[20] LB_A[19] LB_A[18] LB_A[17] LB_A[16] LB_A[15] Signal Name Ball No. E12 C8 U2 R28 P28 R29 AC29 AE28 AJ27 AF27 AJ25 AF24 AH23 AE19 AF21 AJ19 AF18 AJ17 AJ15 AF15 AJ13 AF12 AJ11 AJ9 AF9 AJ7 AF6 AJ5 AJ3 AF1 Signal Name LA_WE1# LA_OE# LB_OE1# MDC MDIO M_CLK M[23]_RXD[1] M[22]_RXD[1] M[21]_RXD[1] M[20]_RXD[1] M[19]_RXD[1] M[18]_RXD[1] M[17]_RXD[1] M[16]_RXD[1] M[15]_RXD[1] M[14]_RXD[1] M[13]_RXD[1] M[12]_RXD[1] M[11]_RXD[1] M[10]_RXD[1] M[9]_RXD[1] M[8]_RXD[1] M[7]_RXD[1] M[6]_RXD[1] M[5]_RXD[1] M[4]_RXD[1] M[3]_RXD[1] M[2]_RXD[1] M[1]_RXD[1] M[0]_RXD[1] Ball No. AA4 AA5 AH7 AE6 AH5 AH2 AF2 AC27 AF29 AG27 AF26 AG25 AG23 AF23 AG21 AH21 AF19 AF17 AG17 AG15 AF14 AG13 AF11 AG11 AG9 AF8 AG7 AF5 AG5 AH3 LB_D[23] LB_D[22] M[4]_RXD[0] M[3]_RXD[0] M[2]_RXD[0] M[1]_RXD[0] M[0]_RXD[0] M[23]_CRS_DV M[22]_CRS_DV M[21]_CRS_DV M[20]_CRS_DV M[19]_CRS_DV M[18]_CRS_DV M[17]_CRS_DV M[16]_CRS_DV M[15]_CRS_DV M[14]_CRS_DV M[13]_CRS_DV M[12]_CRS_DV M[11]_CRS_DV M[10]_CRS_DV M[9]_CRS_DV M[8]_CRS_DV M[7]_CRS_DV M[6]_CRS_DV M[5]_CRS_DV M[4]_CRS_DV M[3]_CRS_DV M[2]_CRS_DV M[1]_CRS_DV Signal Name
Data Sheet
92
Zarlink Semiconductor Inc.
Data Sheet Ball - Signal Name Table (continued)
Ball No. R5 R4 R3 R2 R1 T5 T4 T3 T2 T1 W3 W2 V1 G1 V3 P4 P5 V2 U1 AE8 AJ6 AE5 AJ4 AG1 AE1 AD27 AH28 AG26 AE25 AG24 LB_A[14] LB_A[13] LB_A[12] LB_A[11] LB_A[10] LB_A[9] LB_A[8] LB_A[7] LB_A[6] LB_A[5] LB_A[4] LB_A[3] LB_ADSC# LB_CLK LB_WE# LB_WE0# LB_WE1# LB_OE# LB_OE0# M[5]_TXEN M[4]_TXEN M[3]_TXEN M[2]_TXEN M[1]_TXEN M[0]_TXEN M[23]_TXD[1] M[22]_TXD[1] M[21]_TXD[1] M[20]_TXD[1] M[19]_TXD[1] Signal Name Ball No. AC28 AF28 AH27 AE27 AH25 AE24 AF22 AF20 AE21 AH19 AH20 AH17 AH15 AE15 AH13 AE12 AH11 AH9 AE9 AH8 AF7 AH6 AF4 AH4 AG2 AE2 U26 U25 V26 V25 Signal Name M[23]_RXD[0] M[22]_RXD[0] M[21]_RXD[0] M[20]_RXD[0] M[19]_RXD[0] M[18]_RXD[0] M[17]_RXD[0] M[16]_RXD[0] M[15]_RXD[0] M[14]_RXD[0] M[13]_RXD[0] M[12]_RXD[0] M[11]_RXD[0] M[10]_RXD[0] M[9]_RXD[0] M[8]_RXD[0] M[7]_RXD[0] M[6]_RXD[0] M[5]_RXD[0] M[6]_TXD[0] M[5]_TXD[0] M[4]_TXD[0] M[3]_TXD[0] M[2]_TXD[0] M[1]_TXD[0] M[0]_TXD[0] M25_TXD[15] M25_TXD[14] M25_TXD[13] M25_TXD[12] Ball No. AF3 AD29 AG28 AJ26 AE26 AJ24 AE23 AJ22 AJ20 AE20 AJ18 AJ21 AJ16 AJ14 AE14 AJ12 AE11 AJ10 AJ8 G27 H29 H28 H27 J29 J28 J27 K29 K28 K27 L29
MVTX2603
Signal Name M[0]_CRS_DV M[23]_TXEN M[22]_TXEN M[21]_TXEN M[20]_TXEN M[19]_TXEN M[18]_TXEN M[17]_TXEN M[16]_TXEN M[15]_TXEN M[14]_TXEN M[13]_TXEN M[12]_TXEN M[11]_TXEN M[10]_TXEN M[9]_TXEN M[8]_TXEN M[7]_TXEN M[6]_TXEN M26_RXD[15] M26_RXD[14] M26_RXD[13] M26_RXD[12] M26_RXD[11] M26_RXD[10] M26_RXD[9] M26_RXD[8] M26_RXD[7] M26_RXD[6] M26_RXD[5]
Zarlink Semiconductor Inc.
93
MVTX2603
Ball - Signal Name Table (continued)
Ball No. AE22 AJ23 AG20 AE18 AG18 AE16 AG16 AG14 AE13 AG12 AE10 AG10 AG8 AE7 AG6 AE4 AG4 AG3 AE3 AD28 AG29 AH26 AF25 AH24 AG22 AH22 AE17 AG19 AH18 AF16 Signal Name M[18]_TXD[1] M[17]_TXD[1] M[16]_TXD[1] M[15]_TXD[1] M[14]_TXD[1] M[13]_TXD[1] M[12]_TXD[1] M[11]_TXD[1] M[10]_TXD[1] M[9]_TXD[1] M[8]_TXD[1] M[7]_TXD[1] M[6]_TXD[1] M[5]_TXD[1] M[4]_TXD[1] M[3]_TXD[1] M[2]_TXD[1] M[1]_TXD[1] M[0]_TXD[1] M[23]_TXD[0] M[22]_TXD[0] M[21]_TXD[0] M[20]_TXD[0] M[19]_TXD[0] M[18]_TXD[0] M[17]_TXD[0] M[16]_TXD[0] M[15]_TXD[0] M[14]_TXD[0] M[13]_TXD[0] Ball No. W26 W25 Y27 Y26 AA26 AA25 AB26 AB25 AC26 AC25 AD26 AD25 U27 V29 V28 V27 W29 W28 W27 Y29 Y28 Y25 AA29 AA28 AA27 AB29 AB28 AB27 R26 T25 Signal Name M25_TXD[11] M25_TXD[10] M25_TXD[9] M25_TXD[8] M25_TXD[7] M25_TXD[6] M25_TXD[5] M25_TXD[4] M25_TXD[3] M25_TXD[2] M25_TXD[1] M25_TXD[0] M25_RXD[15] M25_RXD[14] M25_RXD[13] M25_RXD[12] M25_RXD[11] M25_RXD[10] M25_RXD[9] M25_RXD[8] M25_RXD[7] M25_RXD[6] M25_RXD[5] M25_RXD[4] M25_RXD[3] M25_RXD[2] M25_RXD[1] M25_RXD[0] M25_TX_ER M25_TXCLK Ball No. L28 L27 M29 M28 M27 G26 G25 H26 H25 J26 J25 K25 K26 M25 L26 M26 L25 N26 N25 P26 P25 F28 G28 E25 G29 F29 F26 E26 F25 E24 M26_RXD[4] M26_RXD[3] M26_RXD[2] M26_RXD[1] M26_RXD[0] M26_TXD[15] M26_TXD[14] M26_TXD[13] M26_TXD[12] M26_TXD[11] M26_TXD[10] M26_TXD[9] M26_TXD[8] M26_TXD[7] M26_TXD[6] M26_TXD[5] M26_TXD[4] M26_TXD[3] M26_TXD[2] M26_TXD[1] M26_TXD[0] M26_RX_DV M26_RX_ER M26_CRS M26_COL M26_RXCLK M26_TX_EN M26_TX_ER M26_TXCLK Signal Name
Data Sheet
BIST_DONE/TSTOUT[15]
94
Zarlink Semiconductor Inc.
Data Sheet Ball - Signal Name Table (continued)
Ball No. AH16 AH14 AF13 AH12 AF10 AH10 B27 A27 E28 D28 C28 B28 E29 D29 C29 N29 P29 F3 E1 U3 C10 B24 A21 C22 A26 B26 C25 A24 A25 F1 Signal Name M[12]_TXD[0] M[11]_TXD[0] M[10]_TXD[0] M[9]_TXD[0] M[8]_TXD[0] M[7]_TXD[0] G2_LINK#/TSTOUT[8] G2_DPCOL#/TSTOUT[7] G2_RXTX#/TSTOUT[6] G1_LINK#/TSTOUT[5] G1_DPCOL#/TSTOUT[4] G1_RXTX#/TSTOUT[3] LED_BIT/TSTOUT[2] LED_SYN/TSTOUT[1] LED_CLK/TSTOUT[0] GREF_CLK1 GREF_CLK0 SCAN_EN SCLK T_MODE0 T_MODE1 TRUNK2 TRUNK1 TRUNK0 STROBE D0 AUTOFD SCL SDA AVCC Ball No. T26 T28 U28 R25 U29 T29 U18 V12 V13 V14 V15 V16 V17 V18 N14 N15 N16 N17 N18 P12 P13 P14 P15 P16 C19 B19 A19 R13 R14 R15 Signal Name M25_TX_EN M25_RX_DV M25_RX_ER M25_CRS M25_COL M25_RXCLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS OE_CLK2 OE_CLK1 OE_CLK0 VSS VSS VSS Ball No. D24 D25 D26 C26 D27 C27 N12 N13 K17 K18 M10 N10 M20 N20 U10 V10 U20 V20 Y12 Y13 Y17 Y18 K12 K13 M16 M17 M18 F16 F17 N6
MVTX2603
Signal Name BIST_IN_PRC/TST0UT[14] MCT_ERR/TSTOUT[13] FCB_ERR/TSTOUT[12] CHECKSUM_OK/TSTOUT[11] INIT_START/TSTOUT[10] INIT_DONE/TSTOUT[9] VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VDD33 VDD33 VDD33
Zarlink Semiconductor Inc.
95
MVTX2603
Ball - Signal Name Table (continued)
Ball No. D1 D22 E23 E27 N28 N27 F2 G2 B22 A22 C23 B23 A23 C24 D23 T27 F27 C20 B20 A20 C21 RESIN# RESETOUT_ AGND SCANCOL SCANLINK SCANMODE Signal Name Ball No. R16 R17 R18 T12 T13 T14 T15 T16 T17 T18 U12 U13 U14 U15 U16 U17 M12 M13 M14 M15 P17 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. P6 R6 T6 U6 N24 P24 R24 T24 U24 AD13 AD14 AD15 AD16 AD17 F13 F14 F15 R12 B25 E20 P18 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS RESERVED RESERVED VSS Signal Name
Data Sheet
MIRROR5
MIRROR4 MIRROR3 MIRROR2 MIRROR1 MIRROR0 SCANCLK M25_MTXCLK M26_MTXCLK LA_CLK2 LA_CLK1 LA_CLK0 P_D
96
Zarlink Semiconductor Inc.
Data Sheet
14.4 14.4.1 AC/DC Timing Absolute Maximum Ratings
-65C to +150C -40C to +85C +3.0 V to +3.6 V +2.38 V to +2.75 V -0.5 V to (VDD33 + 0.3 V)
MVTX2603
Storage Temperature Operating Temperature Supply Voltage VDD33 with Respect to VSS Supply Voltage VDD with Respect to VSS Voltage on Input Pins
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied.
14.4.2
DC Electrical Characteristics
TAMBIENT = -40C to +85C
VDD33 = 3.0 V to 3.6 V (3.3v +/- 10%) VDD = 2.5V +10% - 5%
14.4.3
Recommended Operation Conditions
Recommended Operation Conditions Table
Preliminary Symbol Parameter Description Min fosc IDD1 IDD2 VOH VOL VIH-TTL VIL-TTL IIH-5VT Frequency of Operation Supply Current - @ 100 MHz (VDD33 =3.3 V) Supply Current - @ 100 MHz (VDD =2.5 V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5V tolerant) Input Low Voltage (TTL 5V tolerant) Input Leakage Current (0.1 V < VIN < VDD33) (all pins except those with internal pull-up/pull-down resistors) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2m/s air flow VDD33 x 70% VDD33 - 0.5 0.5 VDD33 + 2.0 VDD33 x 30% 10 Typ 100 450 1500 Max Unit MHz mA mA V V V V A
CIN COUT CI/O ja ja ja
5 5 7 11.2 10.2 8.9
pF pF pF C/W C/W C/W
Zarlink Semiconductor Inc.
97
MVTX2603
14.5 14.5.1 Local Frame Buffer SBRAM Memory Interface Local SBRAM Memory Interface
Data Sheet
LA_CLK
L1 L2
LA_D[63:0]
Figure 20 - Local Memory Interface - Input setup and hold timing
LA_CLK
L3-max L3-min
LA_D[63:0]
LA_A[20:3]
L4-max L4-min
LA_ADSC#
L6-max L6-min
LA_WE[1:0]# #### LA_OE[1:0]#
L7-max L7-min
L8-max L8-min L9-max L9-min L10-max L10-min
LA_WE#
LA_OE#
Figure 21 - Local Memory Interface - Output valid delay timing
98
Zarlink Semiconductor Inc.
Data Sheet
-100MHz Symbol L1 L2 L3 L4 L6 L7 L8 L9 L10 Parameter Min (ns) LA_D[63:0] input set-up time LA_D[63:0] input hold time LA_D[63:0] output valid delay LA_A[20:3] output valid delay LA_ADSC# output valid delay LA_WE[1:0]#output valid delay LA_OE[1:0]# output valid delay LA_WE# output valid delay LA_OE# output valid delay 4 1.5 1.5 2 1 1 -1 1 1 7 7 7 7 1 7 5 Max (ns)
MVTX2603
Note
CL = 25pf CL = 30pf CL = 30pf CL = 25pf CL = 25pf CL = 25pf CL = 25pf
Table 13 - AC Characteristics - Local frame buffer SBRAM Memory Interface
14.6 14.6.1
Local Switch Database SBRAM Memory Interface Local SBRAM Memory Interface:
LB_CLK
L1 L2
LB_D[63:0]
Figure 22 - Local Memory Interface - Input setup and hold timing
Zarlink Semiconductor Inc.
99
MVTX2603
Data Sheet
LB_CLK
L3-max L3-min
LB_D[31:0]
LB_A[21:2]
L4-max L4-min
LB_ADSC#
L6-max L6-min
LB_WE[1:0]#
L8-max L8-min
LB_OE[1:0]#
L9-max L9-min
LB_WE#
L10-max L10-min L11-max L11-min
LB_OE#
Figure 23 - Local Memory Interface - Output valid delay timing -100MHz Symbol L1 L2 L3 L4 L6 L8 L9 L10 L11 Parameter Min (ns) LB_D[63:0] input set-up time LB_D[63:0] input hold time LB_D[63:0] output valid delay LB_A[20:3] output valid delay LB_ADSC# output valid delay LB_WE[1:0]#output valid delay LB_OE[1:0]# output valid delay LB_WE# output valid delay LB_OE# output valid delay 4 1.5 1.5 2 1 1 -1 1 1 7 7 7 7 1 7 5 CL = 25pf CL = 30pf CL = 30pf CL = 25pf CL = 25pf CL = 25pf CL = 25pf Max (ns) Note
Table 14 - AC Characteristics - Local Switch Database SBRAM Memory Interface
100
Zarlink Semiconductor Inc.
Data Sheet
14.7 14.7.1 AC Characteristics Reduced Media Independent Interface
MVTX2603
M_CLKI
M6-max M6-min
M[23:0]_TXEN
M[23:0] _TXD[1:0]
M7-max M7-min
Figure 24 - AC Characteristics - Reduced Media Independent Interface
M_CLKI
M2 M3 M4 M5
M[23:0]_RXD M[23:0]_CRS_DV
Figure 25 - AC Characteristics - Reduced Media Independent Interface -50MHz Symbol M2 M3 M4 M5 M6 M7 Parameter Min (ns) M[23:0]_RXD[1:0] Input Setup Time M[23:0]_RXD[1:0] Input Hold Time M[23:0]_CRS_DV Input Setup Time M[23:0]_CRS_DV Input Hold Time M[23:0]_TXEN Output Delay Time M[23:0]_TXD[1:0] Output Delay Time 4 1 4 1 2 2 11 11 CL = 20 pF CL = 20 pF Max (ns) Note
Table 15 - AC Characteristics - Reduced Media Independent Interface
Zarlink Semiconductor Inc.
101
MVTX2603
M25_TXCLK
G12-max G12-min G13-max G13-min G14-max G14-min
Data Sheet
M25_TXD [15:0]
M25_TX_EN]
M25_TX_ER
Figure 26 - AC Characteristics- GMII
M25_RXCLK
G1 G2 G3
M25_RXD[15:0] M25_RX_DV
G5
G4
M25_RX_ER
G7
G6
G8
M25_RX_CRS
Figure 27 - AC Characteristics - Gigabit Media Independent Interface -125Mhz Symbol G1 G2 G3 G4 G5 G6 G7 G8 Parameter Min (ns) M[25]_RXD[15:0] Input Setup Times M[25]_RXD[15:0] Input Hold Times M[25]_RX_DV Input Setup Times M[25]_RX_DV Input Hold Times M[25]_RX_ER Input Setup Times M[25]_RX_ER Input Hold Times M[25]_CRS Input Setup Times M[25]_CRS Input Hold Times 2 1 2 1 2 1 2 1 Max (ns) Note
Figure 28 - AC Characteristics - Gigabit Media Independent Interface
102
Zarlink Semiconductor Inc.
Data Sheet
-125Mhz Symbol G12 G13 G14 Parameter Min (ns) M[25]_TXD[15:0] Output Delay Times M[25]_TX_EN Output Delay Times M[25]_TX_ER Output Delay Times 1 1 1 Max (ns) 6 6.5 6
MVTX2603
Note CL = 20pf CL = 20pf CL = 20pf
Figure 28 - AC Characteristics - Gigabit Media Independent Interface (continued)
M25_TXCLK TIMIN M25_TXD [9:0] TIMAX
Figure 29 - Gigabit TBI Interface Transmit Timing
M25_RXCLK
M25_COL T2
M25_RXD[9:0]
T3
T2 T3
Figure 30 - Gigabit TBI Interface Receive Timing Symbol T1 Parameter M25_TXD[9:0] Output Delay Time Min (ns) 1 Max (ns) 6 Note CL = 20pf
Table 16 - Output Delay Timing
Symbol T2 T3
Parameter M25_RXD[9:0] Input Setup Time M25_RXD[9:0] Input Hold Time
Min (ns) 3 3
Max (ns)
Note
Table 17 - Input Setup Timing
Zarlink Semiconductor Inc.
103
MVTX2603
M26_TXCLK
G12-max G12-min G13-max G13-min G14-max G14-min
Data Sheet
M26_TXD [15:0]
M26_TX_EN]
M26_TX_ER
Figure 31 - AC Characteristics- GMII
M26_RXCLK
G1 G2 G3
M26_RXD[15:0] M26_RX_DV
G5
G4
M26_RX_ER
G7
G6
G8
M26_RX_CRS
Figure 32 - AC Characteristics - Gigabit Media Independent Interface
-125Mhz Symbol G1 G2 G3 G4 G5 G6 G7 Parameter Min (ns) M[26]_RXD[15:0] Input Setup Times M[26]_RXD[15:0] Input Hold Times M[26]_RX_DV Input Setup Times M[26]_RX_DV Input Hold Times M[26]_RX_ER Input Setup Times M[26]_RX_ER Input Hold Times M[26]_CRS Input Setup Times 2 1 2 1 2 1 2 Max (ns) Note
Table 18 - AC Characteristics - Gigabit Media Independent Interface
104
Zarlink Semiconductor Inc.
Data Sheet
-125Mhz Symbol G8 G12 G13 G14 Parameter Min (ns) M[26]_CRS Input Hold Times M[26]_TXD[15:0] Output Delay Times M[26]_TX_EN Output Delay Times M[26]_TX_ER Output Delay Times 1 1 1 1 6 6.5 6 Max (ns)
MVTX2603
Note
CL = 20pf CL = 20pf CL = 20pf
Table 18 - AC Characteristics - Gigabit Media Independent Interface (continued)
M26_TXCLK TIMIN M26_TXD [9:0] TIMAX
Figure 33 - Gigabit TBI Interface Transmit Timing
M26_RXCLK
M26_COL T2
M26_RXD[9:0]
T3
T2 T3
Figure 34 - Gigabit TBI Interface Timing Symbol T1 Parameter M26_TXD[9:0] Output Delay Time Min (ns) 1 Max (ns) 6 Note: CL = 20pf
Table 19 - Output Delay Timing
Symbol T2 T3
Parameter M26_RXD[9:0] Input Setup Time M26_RXD[9:0] Input Hold Time 3 3
Min (ns)
Max (ns)
Note
Table 20 - Input Setup Timing
Zarlink Semiconductor Inc.
105
MVTX2603
14.7.2 LED Interface
Data Sheet
LED_CLK
LE5-max LE5-min LE6-max LE6-min
LED_SYN
LED_BIT
Figure 35 - AC Characteristics - LED Interface Variable FREQ. Symbol LE5 LE6 Parameter Min (ns) LED_SYN Output Valid Delay LED_BIT Output Valid Delay -1 -1 Max (ns) 7 7 CL = 30pf CL = 30pf Note
Table 21 - AC Characteristics - LED Interface
14.7.3
SCANLINK SCANCOL Output Delay Timing
SCANCLK
C5-max C5-min
SCANLINK
SCANCOL
C7-max C7-min
Figure 36 - SCANLINK SCANCOL Output Delay Timing
SCANCLK
C1 C2 C3
SCANLINK SCANCOL
C4
Figure 37 - SCANLINK, SCANCOL Setup Timing
106
Zarlink Semiconductor Inc.
Data Sheet
-25MHz Symbol C1 C2 C3 C4 C5 C7 Parameter Min (ns) SCANLINK input set-up time SCANLINK input hold time SCANCOL input setup time SCANCOL input hold time SCANLINK output valid delay SCANCOL output valid delay 20 2 20 1 0 0 10 10 Max (ns)
MVTX2603
Note:
CL = 30pf CL = 30pf
Table 22 - SCANLINK, SCANCOL Timing
14.7.4
MDIO Input Setup and Hold Timing
MDC
D1 D2
MDIO
Figure 38 - MDIO Input Setup and Hold Timing
MDC
D3-max D3-min
MDIO
Figure 39 - MDIO Output Delay Timing
1MHz Symbol D1 D2 D3 Parameter Min (ns) MDIO input setup time MDIO input hold time MDIO output delay time 10 2 1 Table 23 - MDIO Timing 20 CL = 50pf Max (ns) Note
Zarlink Semiconductor Inc.
107
MVTX2603
14.7.5 I2C Input Setup Timing
Data Sheet
SCL
S1 S2
SDA
Figure 40 - I2 C Input Setup Timing
SCL
S3-max S3-min
SDA
Figure 41 - I2C Output Delay Timing
50KHz Symbol S1 S2 S3* Parameter Min (ns) SDA input setup time SDA input hold time SDA output delay time 20 1 4 usec 6 usec CL = 30pf Max (ns) Note
* Open Drain Output. Low to High transistor is controlled by external pullup resistor. Table 24 - I2C Timing
108
Zarlink Semiconductor Inc.
Data Sheet
14.7.6 Serial Interface Setup Timing
MVTX2603
STROBE
D1 D2
D4 D1 D2
D5
D0
Figure 42 - Serial Interface Setup Timing
STROBE
D3-max D3-min
AutoFd
Figure 43 - Serial Interface Output Delay Timing
Symbol D1 D2 D3 D4 D5 D0 setup time D0 hold time
Parameter
Min (ns) 20 3s 1 5s 5s
Max (ns)
Note
AutoFd output delay time Strobe low time Strobe high time
50
CL = 100pf
Table 25 - Serial Interface Timing
Zarlink Semiconductor Inc.
109
MVTX2603
Data Sheet
110
Zarlink Semiconductor Inc.
E1
E
DIMENSION A A1 A2 D D1 E E1 b e
MIN MAX 2.20 2.46 0.50 0.70 1.17 REF 37.70 37.30 34.50 REF 37.70 37.30 34.50 REF 0.60 0.90 1.27 553 Conforms to JEDEC MS - 034
e D D1
A2 b
NOTE:
1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
ISSUE ACN DATE APPRD.
Previous package codes:
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